# US 2015/0146471 A1 · Anti-fuse array of semiconductor device and method for operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0146471 A1 - Document ID: US20150146471A1 - Status: Published application - Kind: A1 - Application number: 14/267,810 - Filed: 2014-05-01 - Published: 2015-05-28 - Earliest claimed: 2013-11-26 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Sung Su KIM - Web page: https://patentgrep.com/patent/US20150146471A1 ## CPC - H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive} - G11C 17/16: using electrically-fusible links - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction. ## Claims ### Claim 1 An anti-fuse array comprising: a plurality of first transistors having a matrix structure over a semiconductor substrate, the plurality of first transistors including a plurality of gate lines extending along a first direction, a plurality of channel lines extending along a second direction; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of gate lines; and a plurality of third transistors respectively disposed at second ends of the plurality of channel lines. ### Claim 2 (depends on 1) The anti-fuse array according to claim 1, wherein the plurality of first transistors is used as program transistors, and the pluralities of second and third transistors are used as select transistors. ### Claim 3 (depends on 1) The anti-fuse array according to claim 1, wherein the plurality of first transistors includes: the plurality of channel lines spaced apart from each other by a predetermined distance; a plurality of gate insulation film lines including a plurality of gate insulation films and extending in the first direction to overlap portions of the plurality of channel lines; and the plurality of gate lines disposed over the plurality of gate insulation film lines to overlap portions of the plurality of channel lines, wherein the plurality of gate insulation films disposed between the channel lines and the gate lines. ### Claim 4 (depends on 1) The anti-fuse array according to claim 1, wherein the plurality of first transistors includes: the plurality of channel lines spaced apart from each other by a predetermined distance; a plurality of gate insulation film lines including the plurality of gate insulation films and disposed perpendicular to the plurality of channel lines; and the plurality of gate lines disposed over the gate insulation film lines. ### Claim 5 (depends on 1) The anti-fuse array according to claim 1, wherein the plurality of channel lines is formed by ion implantation. ### Claim 6 (depends on 1) The anti-fuse array according to claim 1, wherein at least one third transistor among the plurality of third transistors includes: a first channel region disposed in the semiconductor substrate; a second channel region disposed in the semiconductor substrate and spaced apart from the first channel region by a predetermined distance, the second channel region being coupled to a portion of a channel line; a select gate insulation film disposed over a region between the first channel region and the second channel region; and a gate electrode disposed over the select gate insulation film. ### Claim 7 (depends on 6) The anti-fuse array according to claim 6, wherein the first channel region and the second channel region are simultaneously formed by ion implantation when the corresponding channel line is formed. ### Claim 8 (depends on 1) The anti-fuse array according to claim 1, wherein the first direction is substantially perpendicular to the second direction. ### Claim 9 (depends on 1) The anti-fuse array according to claim 1, wherein at least one second transistor among the plurality of second transistors includes: first and second channel regions disposed in the semiconductor substrate and spaced apart from each other by a predetermined distance; a select gate insulation film disposed over a region between the first and second channel regions; and a gate electrode disposed over the gate insulation film. ### Claim 10 (depends on 4) The anti-fuse array according to claim 4, wherein at least one second transistor among the plurality of second transistors is spaced apart from an end portion of a gate line by a predetermined distance in a longitudinal direction thereof. ### Claim 11 (depends on 4) The anti-fuse array according to claim 4, wherein the plurality of third transistors is electrically coupled to the plurality of channel lines, respectively. ### Claim 12 (depends on 4) The anti-fuse array according to claim 4, further comprising: a metal structure configured to electrically interconnect a second transistor among the plurality of second transistors and a first group of the plurality of first transistors. ### Claim 13 (depends on 12) The anti-fuse array according to claim 12, wherein the metal structure includes: a first metal contact coupled to a gate line of the first group of the plurality of first transistors; a second metal contact coupled to a channel region of the second transistor; and a metal line configured to interconnect the first metal contact and the second metal contact. ### Claim 14 (depends on 4) The anti-fuse array according to claim 4, wherein the anti-fuse array further comprises a plurality of metal structures, and wherein the plurality of gate lines is electrically coupled to the plurality of metal structures, respectively. ### Claim 15 A method for operating an anti-fuse array which includes a plurality of first transistors formed as a matrix structure over a semiconductor substrate, a plurality of second transistors respectively formed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure, and a plurality of third transistors respectively formed at second ends of the plurality of first transistors along a second direction, the method comprising: applying a first voltage to the plurality of first transistors using a first transistor among the plurality of second transistors; applying a second voltage to the plurality of first transistors using a second transistor among the plurality of third transistors; and rupturing a third transistor among the first plurality of transistors located at an intersection of a gate line coupled to the first transistor and a channel line coupled to the second transistor due to a voltage level difference across a gate insulation film of the third transistor corresponding to a difference between the first voltage and the second voltage. ### Claim 16 (depends on 15) The method according to claim 15, wherein, during a program operation, the first voltage is a power-supply voltage (VDD), and the second voltage is a ground voltage. ### Claim 17 (depends on 15) The method according to claim 15, further comprising: applying a third voltage to the plurality of first transistors using a fourth transistor among the plurality of second transistors, and applying a fourth voltage to the plurality of first transistors using a fifth transistor among the plurality of third transistors, and performing a read operation on a sixth transistor among the plurality of first transistors located at an intersection of a gate line coupled to the fourth transistor and a channel line coupled to the fifth transistor. ### Claim 18 (depends on 17) The method according to claim 17, wherein, during the read operation, the third voltage is a read voltage, and the fourth voltage is a ground voltage. ### Claim 19 (depends on 15) The method according to claim 15, wherein the first plurality of transistors is used as program transistors, and the second and third pluralities of transistors are used as select transistors. ### Claim 20 (depends on 15) The method according to claim 15, further comprising: after rupturing of the third transistor, rupturing a fourth transistor among the first plurality of transistors, the fourth transistor disposed closer to the third plurality of transistors than the third transistor in the second direction.