# US 2015/0145127 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0145127 A1 - Document ID: US20150145127A1 - Status: Published application - Kind: A1 - Application number: 14/611,354 - Filed: 2015-02-02 - Published: 2015-05-28 - Earliest claimed: 2012-03-27 - Assignees: Mediatek Inc. - Applicants: MediaTek Inc. - Inventors: Wen-Sung HSU; Tzu-Hung LIN; Ta-Jen YU - Web page: https://patentgrep.com/patent/US20150145127A1 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 74/134: {the encapsulations being in grooves in the semiconductor body} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 74/147: {the encapsulations being multilayered} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/072: {of bump connectors} - H10W 72/07254: {changes in dispositions} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/30: Die-attach connectors - H10W 72/354: {comprising polymers} - H10W 72/387: {Flow barriers} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A conductive pillar bump is disposed on the conductive trace, wherein the conductive bump is coupled to a die. In another configuration, a first conductive trace is disposed on the substrate, and a second conductive trace is disposed on the substrate. In the second configuration, a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die. A first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate, and a die is disposed over the first conductive trace. ## Claims ### Claim 1 A semiconductor package, comprising: a substrate; a conductive trace disposed on the substrate; and a conductive pillar bump disposed on the conductive trace, wherein the conductive bump is coupled to a die. ### Claim 2 (depends on 1) The semiconductor package as claimed in claim 1, wherein conductive trace comprising a first portion having a first width and a second portion having a second width, and the conductive pillar bump is disposed on the second portion of the conductive trace. ### Claim 3 (depends on 1) The semiconductor package as claimed in claim 1, wherein the semiconductor package comprises a plurality of conductive pillar bumps disposed on the second portion of the conductive trace. ### Claim 4 (depends on 1) The semiconductor package as claimed in claim 1, wherein the semiconductor package further comprises a metal pad located between the conductive trace and the substrate. ### Claim 5 (depends on 4) The semiconductor package as claimed in claim 4, wherein the semiconductor package further comprises a metal pad located between the conductive pillar bump and the conductive trace. ### Claim 6 (depends on 1) The semiconductor package as claimed in claim 1, wherein the conductive trace comprises a plurality of conductive layers and a metal pad, wherein the metal pad is sandwiched by the plurality of conductive layers ### Claim 7 A semiconductor package, comprising: a substrate; a first conductive trace disposed on the substrate; a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die; a first conductive structure disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate; and a die disposed over the first conductive trace. ### Claim 8 (depends on 7) The semiconductor package as claimed in claim 7, further comprising: a solder resistance layer disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. ### Claim 9 (depends on 7) The semiconductor package as claimed in claim 7, wherein the first conductive structure contacts the second conductive trace, overlapping with the conductive pillar bump. ### Claim 10 (depends on 7) The semiconductor package as claimed in claim 7, further comprising: a second conductive structure disposed overlapping a portion of the second conductive trace and the semiconductor die or a portion of the second conductive trace and the substrate, wherein the portion of the second conductive trace is away from the conductive pillar bump. ### Claim 11 (depends on 10) The semiconductor package as claimed in claim 10, wherein the third conductive structure or the second conductive structure comprises a single-layer structure or a multi-layer structure. ### Claim 12 (depends on 11) The semiconductor package as claimed in claim 11, wherein the single-layer structure comprises a trace or a pad. ### Claim 13 (depends on 11) The semiconductor package as claimed in claim 11, wherein the multi-layer structure is a stack of traces, pads or combinations thereof. ### Claim 14 (depends on 7) The semiconductor package as claimed in claim 7, wherein the first conductive structure is a polygonal shape, a rounded shape, or a drop shape. ### Claim 15 (depends on 7) The semiconductor package as claimed in claim 7, wherein the second conductive trace comprises signal traces or ground traces. ### Claim 16 (depends on 8) The semiconductor package as claimed in claim 8, wherein the solder resistance layer is disposed away from a portion of the second conductive trace, which overlaps with the conductive pillar bump, by a distance. ### Claim 17 (depends on 8) The semiconductor package as claimed in claim 8, further comprising an underfill material filling a gap between the substrate and the semiconductor die, covering the solder resistance layer. ### Claim 18 (depends on 8) The semiconductor package as claimed in claim 8, wherein the extending portion of the solder resistance layer and the portion of the first conductive trace collectively have a T-shaped cross section. ### Claim 19 (depends on 8) The semiconductor package as claimed in claim 8, wherein the extending portion of the solder resistance layer is below the semiconductor die and within a projection area of the semiconductor die. ### Claim 20 (depends on 17) The semiconductor package as claimed in claim 17, wherein a portion of a bottom surface of the extending portion of the solder resistance layer is exposed from the portion of the first conductive trace. ### Claim 21 (depends on 20) The semiconductor package as claimed in claim 20, wherein the portion of the bottom surface of the extending portion of the solder resistance layer is wrapped by the underfill material. ### Claim 22 (depends on 8) The semiconductor package as claimed in claim 8, wherein the extending portion of the solder resistance layer has a vertical sidewall extruding over to an adjacent vertical sidewall of the portion of the first conductive trace. ### Claim 23 (depends on 8) The semiconductor package as claimed in claim 8, wherein the extending portion of the solder resistance layer extends along the first conductive trace and over a die attach surface of the semiconductor die.