# US 2015/0145104 A1 · Integrated capacitor and method for producing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0145104 A1 - Document ID: US20150145104A1 - Status: Published application - Kind: A1 - Application number: 14/549,791 - Filed: 2014-11-21 - Published: 2015-05-28 - Earliest claimed: 2013-11-22 - Assignees: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V. - Applicants: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V. - Inventors: Anton BAUER; Tobias ERLBACHER; Holger SCHWARZMANN - Web page: https://patentgrep.com/patent/US20150145104A1 ## CPC - H10D 1/692: {Electrodes} - H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 84/206: {of combinations of capacitors and resistors} - H10D 84/212: {of only capacitors} - H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates} - H10P 14/40: of conductive or resistive materials - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated capacitor includes a substrate with a first main surface area and an opposing second main surface area. A capacitor structure with a dielectric layer is integrated in the first main surface area. A compensation structure with a compensation layer is integrated in the second main surface area. The ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure. ## Claims ### Claim 1 Integrated capacitor, comprising: a substrate with a first main surface area and an opposing second main surface area; a capacitor structure with a dielectric layer, wherein the capacitor structure is integrated in the first main surface area; and a compensation structure with a compensation layer that is integrated in the second main surface area; wherein a ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure. ### Claim 2 (depends on 1) Integrated capacitor according to claim 1, wherein the compensation structure is implemented to at least partly compensate, based on a material tension between the compensation layer and the substrate, material tension between the dielectric layer and the substrate in the substrate, such that a deformation of the substrate induced by the mechanical tension between the dielectric layer and the substrate is reduced. ### Claim 3 (depends on 1) Integrated capacitor according to claim 1, wherein the surface enlargement of the first main surface area relates to an area of the capacitor structure covered by the dielectric layer, and wherein the surface enlargement of the second main surface area relates to an area of the compensation structure covered by the compensation layer. ### Claim 4 Integrated capacitor comprising: a substrate with a first main surface area and an opposing second main surface area; a capacitor structure with a dielectric layer, wherein the capacitor structure is integrated in the first main surface area; and a compensation structure with a compensation layer, wherein the compensation structure is integrated in the second main surface area; wherein the compensation structure is implemented to at least partly compensate, based on a material tension between the compensation layer and the substrate, material tension between the dielectric layer and the substrate in the substrate, such that a deformation of the substrate induced by the mechanical tension between the dielectric layer and the substrate is reduced. ### Claim 5 (depends on 4) Integrated capacitor according to claim 4, wherein a ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure. ### Claim 6 (depends on 5) Integrated capacitor according to claim 5, wherein the surface enlargement of the first main surface area relates to an area of the capacitor structure covered by the dielectric layer, and wherein the surface enlargement of the second main surface area relates to an area of the compensation structure covered by the compensation layer. ### Claim 7 (depends on 1) Integrated capacitor according to claim 1, wherein the dielectric layer comprises silicon nitride and comprises a thickness of more than 500 nm, or wherein the dielectric layer comprises an equivalent oxide thickness (EOT) of more than 280 nm. ### Claim 8 (depends on 1) Integrated capacitor according to claim 1, wherein the compensation structure comprises a compensation material, which is isolated from the substrate by means of the compensation layer. ### Claim 9 (depends on 8) Integrated capacitor according to claim 8, wherein the compensation material and an electrode material in the capacitor structure comprise the same materials, or wherein the dielectric layer and the compensation layer comprise the same materials. ### Claim 10 (depends on 1) Integrated capacitor according claim 1, wherein a first electrode terminal is arranged at the capacitor structure and a second electrode terminal at the substrate. ### Claim 11 (depends on 10) Integrated capacitor according to claim 10, further comprising a third electrode terminal arranged at the compensation structure. ### Claim 12 (depends on 1) Integrated capacitor according to claim 1, wherein the compensation structure is short-circuited to the substrate. ### Claim 13 (depends on 1) Integrated capacitor according to claim 1, wherein the capacitor structure comprises a hole structure with a plurality of holes, a trench structure with a plurality of trenches, a column structure with a plurality of columns or a ring structure. ### Claim 14 (depends on 1) Integrated capacitor according to claim 1, wherein the compensation structure comprises a hole structure with a plurality of holes, a trench structure with a plurality of trenches, a column structure with a plurality of columns or a ring structure. ### Claim 15 (depends on 1) Integrated capacitor according to claim 1, wherein the capacitor structure in the first main surface area and the compensation structure in the second main surface area are arranged opposite to one another at the substrate and are implemented equally within a tolerance range. ### Claim 16 Integrated capacitor, comprising: a substrate with a first main surface area and an opposing second main surface area; a capacitor structure with a dielectric layer, wherein the capacitor structure is integrated in the first main surface area; and a compensation structure with a compensation layer that is integrated in the second main surface area; wherein a ratio between a surface enlargement of the second main surface area effected by the compensation structure with regard to a theoretical surface of the substrate in the second main surface area when the compensation structure is absent, corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure with regard to a theoretical surface of the substrate in the first main surface area when the capacitor structure is absent; wherein structures of the compensation structure are arranged laterally offset with respect to structures of the capacitor structure. ### Claim 17 (depends on 16) Integrated capacitor according to claim 16, wherein the compensation structure is implemented to at least partly compensate, based on a material tension between the compensation layer and the substrate, material tension between the dielectric layer and the substrate in the substrate, such that a deformation of the substrate induced by the material tension between the dielectric layer and the substrate is reduced. ### Claim 18 (depends on 16) Integrated capacitor according to claim 16, wherein the surface enlargement of the first main surface area relates to the theoretical surface of the substrate in the first main surface area when the capacitor structure is absent, and to an area of the capacitor structure covered by the dielectric layer, and wherein the surface enlargement of the second main surface area relates to the theoretical surface of the substrate in the second main surface area when the compensation structure is absent, and to an area of the compensation structure covered by the compensation layer. ### Claim 19 Integrated capacitor comprising: a substrate with a first main surface area and an opposing second main surface area; a capacitor structure with a dielectric layer, wherein the capacitor structure is integrated in the first main surface area; and a compensation structure with a compensation layer, wherein the compensation structure is integrated in the second main surface area; wherein the compensation structure is implemented to at least partly compensate, based on a material tension between the compensation layer and the substrate, material tension between the dielectric layer and the substrate in the substrate, such that a deformation of the substrate induced by the material tension between the dielectric layer and the substrate is reduced; wherein structures of the compensation structure are arranged laterally offset with respect to structures of the capacitor structure. ### Claim 20 (depends on 19) Integrated capacitor according to claim 19, wherein a ratio between a surface enlargement of the second main surface area effected by the compensation structure with regard to a theoretical surface of the substrate in a second main surface area when the compensation structure is absent, corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure with regard to a theoretical surface of the substrate in the first main surface area when the capacitor structure is absent. ### Claim 21 (depends on 20) Integrated capacitor according to claim 20, wherein the surface enlargement of the first main surface area relates to the theoretical surface of the substrate in the first main surface area when the capacitor structure is absent, and to an area of the capacitor structure covered by the dielectric layer, and wherein the surface enlargement of the second main surface area relates to the theoretical surface of the substrate in the second main surface area when the compensation structure is absent, and to an area of the compensation structure covered by the compensation layer. ### Claim 22 (depends on 16) Integrated capacitor according to claim 16, wherein the dielectric layer comprises silicon nitride and comprises a thickness of more than 500 nm, or wherein the dielectric layer comprises an equivalent oxide thickness (EOT) of more than 280 nm with regard to silicon dioxide. ### Claim 23 (depends on 1) Usage of the capacitor according to claim 1 in a power module or in a packaged semiconductor device. ### Claim 24 (depends on 23) Usage of the capacitor according to claim 23, wherein the same is implemented as damping element or coupling capacitor within the power module or the packaged semiconductor device. ### Claim 25 (depends on 23) Usage of the capacitor according to claim 23, wherein the power module or the packaged semiconductor device with the integrated capacitor is connected to an energy source to absorb electric energy from the network. ### Claim 26 (depends on 1) Usage of the capacitor according to claim 1, comprising a semiconductor device in a common package. ### Claim 27 Method for producing an integrated capacitor, comprising: providing a substrate with a first main surface area and an opposing second main surface area; forming a capacitor structure with a dielectric layer in the first main surface area; and forming a compensation structure with a compensation layer in the second main surface area; wherein a ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure; or wherein the compensation structure is implemented to at least partly compensate, based on a material tension between the compensation layer and the substrate, material tension between the dielectric layer and the substrate in the substrate, such that a deformation of the substrate induced by the mechanical tension between the dielectric layer and the substrate is reduced. ### Claim 28 Method for producing an integrated capacitor, comprising: providing a substrate with a first main surface area and an opposing second main surface area; forming a capacitor structure with a dielectric layer in the first main surface area; and forming a compensation structure with a compensation layer in the second main surface area, such that structures of the compensation structure are arranged laterally offset with regard to structures of the capacitor structure; wherein a ratio between a surface enlargement of the second main surface area effected by the compensation structure with regard to a theoretical surface of the substrate in the second main surface area when the compensation structure is absent, corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure with regard to a theoretical surface of the substrate in the first main surface area when the capacitor structure is absent; or wherein the compensation structure is implemented to at least partly compensate, based on a material tension between the compensation layer and the substrate, material tension between the dielectric layer and the substrate in the substrate, such that a deformation of the substrate induced by the mechanical tension between the dielectric layer and the substrate is reduced.