# US 2015/0145052 A1 · Circuit and Method for Improving ESD Tolerance and Switching Speed > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0145052 A1 - Document ID: US20150145052A1 - Status: Published application - Kind: A1 - Application number: 14/521,378 - Filed: 2014-10-22 - Published: 2015-05-28 - Earliest claimed: 2013-11-20 - Assignees: Peregrine Semiconductor Corporation - Applicants: Peregrine Semiconductor Corporation - Inventors: Eric S. Shapiro; Matt Allison - Web page: https://patentgrep.com/patent/US20150145052A1 ## CPC - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 89/813: {specially adapted to provide an electrical current path other than the field-effect induced current path} - H10D 89/911: {using passive elements as protective elements} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance. ## Claims ### Claim 1 An electronic circuit including: (a) a field effect transistor (FET) having a gate, a drain, a source, and a body; (b) a gate resistor series connected to the gate of the FET; (c) an accumulated charge sink (ACS) circuit connected to the body of the FET; and (d) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET. ### Claim 2 (depends on 1) The electronic circuit of claim 1, wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit. ### Claim 3 (depends on 1) The electronic circuit of claim 1, wherein the resistance of the ACS resistance has at least 10 times the resistance of the gate resistor. ### Claim 4 (depends on 1) The electronic circuit of claim 1, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET between the gate resistor and the gate. ### Claim 5 (depends on 1) The electronic circuit of claim 1, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET at a node opposite to the connection of the gate resistor to the gate. ### Claim 6 (depends on 1) The electronic circuit of claim 1, wherein the ACS circuit is a diode. ### Claim 7 An integrated circuit including at least two stacked field effect transistors (FET) each having a gate, a drain, a source, and a body, each FET further including: (a) a gate resistor series connected to the gate of such FET; (b) an accumulated charge sink (ACS) circuit connected to the body of such FET; and (c) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit. ### Claim 9 (depends on 7) The integrated circuit of claim 7, wherein the resistance of the ACS resistance has at least 10 times the resistance of the gate resistor. ### Claim 10 (depends on 7) The integrated circuit of claim 7, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET between the gate resistor and the gate. ### Claim 11 (depends on 7) The integrated circuit of claim 7, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate. ### Claim 12 (depends on 7) The integrated circuit of claim 7, wherein the ACS circuit is a diode. ### Claim 13 (depends on 7) The integrated circuit of claim 7, wherein the integrated circuit is fabricated on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate. ### Claim 14 A method for improving ESD tolerance and switching speed in an electronic circuit that includes an ACS circuit, including adding a resistance in series with the ACS circuit. ### Claim 15 A method for improving electrostatic discharge tolerance and switching speed in an integrated circuit, including: (a) fabricating an integrated circuit including a field effect transistor (FET) having a gate, a drain, a source, and a body; (b) connecting a gate resistor in series with the gate of the FET; (c) connecting an accumulated charge sink (ACS) circuit to the body of the FET; (d) connecting an ACS resistance in series with the ACS circuit; and (e) connecting the series-connected ACS resistance and the ACS circuit to the gate resistor. ### Claim 16 (depends on 15) The method of claim 15, further including sizing the resistance of the ACS resistance to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit. ### Claim 17 (depends on 15) The method of claim 15, further including setting the resistance of the ACS resistance to be at least 10 times the resistance of the gate resistor. ### Claim 18 (depends on 15) The method of claim 15, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET between the gate resistor and the gate. ### Claim 19 (depends on 15) The method of claim 15, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of the FET at a node opposite to the connection of the gate resistor to the gate. ### Claim 20 (depends on 15) The method of claim 15, wherein the ACS circuit is a diode. ### Claim 21 (depends on 15) The method of claim 15, wherein the step of fabricating an integrated circuit includes fabricating the integrated circuit on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate. ### Claim 22 An integrated circuit including at least one field effect transistor (FET) configured to switch or process a radio frequency signal, each FET having a gate, a drain, a source, and a body, each FET further including: (a) a gate resistor series connected to the gate of such FET at a first node and configured to be coupled to a control signal at a second node; (b) an accumulated charge sink (ACS) diode connected to the body of such FET; and (c) at least one ACS resistance series connected to the ACS diode, wherein the series-connected at least one ACS resistance and the ACS diode are connected to the gate resistor of such FET and the at least one ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS diode. ### Claim 23 (depends on 22) The integrated circuit of claim 22, wherein the total resistance of the at least one ACS resistance has at least 10 times the resistance of the gate resistor. ### Claim 24 (depends on 22) The integrated circuit of claim 22, wherein the series-connected at least one ACS resistance and the ACS diode are connected to the first node. ### Claim 25 (depends on 22) The integrated circuit of claim 22, wherein the series-connected at least one ACS resistance and the ACS diode are connected to the second node. ### Claim 26 (depends on 22) The integrated circuit of claim 22, wherein the integrated circuit is fabricated on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate.