# US 2015/0145014 A1 · Vertical memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0145014 A1 - Document ID: US20150145014A1 - Status: Published application - Kind: A1 - Application number: 14/471,778 - Filed: 2014-08-28 - Published: 2015-05-28 - Earliest claimed: 2013-11-27 - Inventors: Su-Jin SHIN; Dong-Chul YOO; Ki-Hyun HWANG - Web page: https://patentgrep.com/patent/US20150145014A1 ## CPC - H10B 43/00: EEPROM devices comprising charge-trapping gate insulators - H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/689: {Vertical floating-gate IGFETs} - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - H10D 64/681: {having a compositional variation, e.g. multilayered} - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction. ## Claims ### Claim 1 A vertical memory device, comprising: a substrate including a central region and a peripheral region; at least one first cell block on the central region, the first cell block including a first channel extending in a first direction vertical to a top surface of the substrate, and first gate lines surrounding the first channel and spaced apart from each other in the first direction; and at least one second cell block on the peripheral region, the second cell block having a width greater than a width of the first cell block, the second block including a second channel extending in the first direction vertical to the top surface of the substrate, and second gate lines surrounding the second channel and spaced apart from each other in the first direction. ### Claim 2 (depends on 1) The vertical memory device of claim 1, wherein the first cell block includes a plurality of first channels, the plurality of first channels form a first channel bundle, the second cell block includes a plurality of second channels, and the plurality of second channels form a second channel bundle. ### Claim 3 (depends on 2) The vertical memory device of claim 2, wherein a number of the second channel bundles included in the second cell block is greater than a number of the first channel bundles included in the first cell block. ### Claim 4 (depends on 3) The vertical memory device of claim 3, wherein the first cell block includes one first channel bundle, and the second cell block includes at least two second channel bundles. ### Claim 5 (depends on 3) The vertical memory device of claim 3, wherein the second cell block further includes a separation layer pattern between the two of the at least two channel bundles, the two of the at least two channel bundles neighboring each other. ### Claim 6 (depends on 5) The vertical memory device of claim 5, wherein the first gate lines of the first cell block include a first ground selection line (GSL), at least one first word line, and a first string selection line (SSL) sequentially stacked on each other from the top surface of the substrate, the second gate lines of the second cell block include a second ground selection line (GSL), at least one second word line, and a second string selection line (SSL) sequentially stacked on each other from the top surface of the substrate, and the separation layer pattern extends through the second SSL of the second cell block. ### Claim 7 (depends on 1) The vertical memory device of claim 1, wherein the at least one first cell block is a plurality of first cell blocks on the central region, and the at least one second cell block is one second cell block on the peripheral region. ### Claim 8 (depends on 1) The vertical memory device of claim 1, wherein the second cell block further includes a supporting pattern at a central portion of the second gate lines at each level of the second gate lines spaced apart from each other in the first direction. ### Claim 9 (depends on 8) The vertical memory device of claim 8, wherein the first cell block further includes first insulating interlayer patterns stacked on each other between the first gate lines in the first direction, the second cell block further includes second insulating interlayer patterns stacked on each other between the second gate lines in the first direction, the first and second insulating interlayer patterns include silicon oxide, and the supporting pattern includes silicon nitride. ### Claim 10 (depends on 1) The vertical memory device of claim 1, wherein further comprising: filling layer patterns on the substrate, wherein the at least one first cell block is a plurality of first cell blocks on the central region, the at least one second cell block is one or a plurality of second cell blocks on the peripheral region, and the filling layer patterns extend between at least one of the plurality of first cell blocks and the plurality of second cell blocks. ### Claim 11 (depends on 10) The vertical memory device of claim 10, wherein the at least one second cell block is the plurality of second cell blocks, the filling layer patterns extend between the plurality of first cell blocks and the plurality of second cell blocks, a distance between the filling layer patterns on the peripheral region that neighbor each other is greater than a distance between the filling layer patterns on the central region that neighbor each other. ### Claim 12 (depends on 10) The vertical memory device of claim 10, wherein the first cell block and the second cell block are spaced apart from each other in a second direction, the first and second gate lines extend in a third direction, the filling layer patterns extend in the third direction, the second direction and third direction are parallel to the top surface of the substrate, and the second direction and the third direction are perpendicular to each other. ### Claim 13 (depends on 1) The vertical memory device of claim 1, wherein the peripheral region is a dummy region. ### Claim 14 (depends on 13) The vertical memory device of claim 13, further comprising: a bit line selectively and electrically connected to the first channel of the first cell block. ### Claim 15 A vertical memory device, comprising: a substrate including a central region and a peripheral region; a plurality of first cell blocks on the central region, the first cell block including a first channel extending in a first direction vertical to a top surface of the substrate, and first gate lines surrounding the first channel and spaced apart from each other in the first direction; a plurality of second cell blocks on the peripheral region, the second cell block including a second channel extending in the first direction vertical to the top surface of the substrate, and second gate lines surrounding the second channel and spaced apart from each other in the first direction, and a distance between the plurality of second cell blocks that neighbor each other is greater than a distance between the plurality of first cell blocks that neighbor each other. ### Claim 16 (depends on 15) The vertical memory device of claim 15, wherein the plurality of first cell blocks and the plurality of second cell blocks have a same width. ### Claim at position 17 17-25. (canceled) ### Claim 26 A vertical memory device, comprising: a substrate including a central region and a peripheral region; and a stacked structure on the substrate, the stacked structure including a plurality of channels extending in a first direction through a plurality of gate lines and a plurality of insulating layers alternately stacked on each other on the substrate, the plurality of channels being spaced apart from each other, the plurality of gate lines and insulating layers defining openings that expose the substrate and separate the stacked structure into a plurality of first cell blocks on the central region and at least one second cell block on the peripheral region of the substrate, each one of the at least one second cell block having one of, a width that is different than a width of any one of the plurality of first cell blocks, and a different separation distance from an adjacent one of the plurality of first cell blocks compared to a separation distance between the plurality of first cell blocks that neighbor each other. ### Claim 27 (depends on 26) The vertical memory device of claim 26, wherein each one of the at least one second cell block has the width that is different than the width of any one of the plurality of first cell blocks, the width of each one of the at least one second cell block is greater than the width of any one of the plurality of first cell blocks, and a number of the channels per each one of the at least one second cell block is greater than a number of the channels per any one of the plurality of first cell blocks. ### Claim 28 (depends on 26) The vertical memory device of claim 26, further comprising: at least one bit line electrically connected to the plurality of channels in the plurality of first cell blocks that are below the bit line, wherein the stacked structure includes a plurality of dielectric structures, each one of the plurality of dielectric structures surrounds a corresponding one of the plurality of channels, and the plurality of dielectric structures extend the first direction through the plurality of gate lines and insulating layers. ### Claim 29 (depends on 26) The vertically memory device of claim 26, wherein the at least one second cell block is a plurality of second cell blocks on the peripheral region of the substrate, a separation distance between the plurality of second cell blocks that neighbor each other is greater than the separation distance between the plurality of first cell blocks that neighbor each other, and the openings that separate the stacked structure into the plurality of second blocks have a greater width than the openings that separate the stacked structure into the plurality of first blocks.