# US 2015/0145003 A1 · Finfet semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2015/0145003 A1
- Document ID: US20150145003A1
- Status: Published application
- Kind: A1
- Application number: 14/534,453
- Filed: 2014-11-06
- Published: 2015-05-28
- Earliest claimed: 2013-11-26
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Mark S. Rodder; Borna J. Obradovic; Robert C. Bowen
- Web page: https://patentgrep.com/patent/US20150145003A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.

## Claims

### Claim 1

A finFET semiconductor device, comprising:
an insulator layer;
a bottom semiconductor layer on the insulator layer, the bottom semiconductor layer comprising a first percentage of a first semiconductor material and a second semiconductor material;
a channel fin on the bottom semiconductor layer, the channel fin comprising a second percentage of the first semiconductor material and the second semiconductor material, wherein the second percentage of the first semiconductor material in the channel fin is less than the first percentage of the first semiconductor material in the bottom semiconductor layer;
a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, the source region comprising a third percentage of the first semiconductor material and the second semiconductor material, wherein the third percentage of the first semiconductor material in the source region is greater than the second percentage of the first semiconductor material in the channel fin; and
a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin that is opposite the first side, the drain region comprising a fourth percentage of the first semiconductor material and the second semiconductor material, wherein the fourth percentage of the first semiconductor material in the drain region is greater than the second percentage of the first semiconductor material in the channel fin.

### Claim 2 (depends on 1)

The finFET semiconductor device of claim 1, wherein the first semiconductor material is silicon and the second semiconductor material is germanium.

### Claim 3 (depends on 1)

The finFET semiconductor device of claim 1, wherein the third and fourth percentages of the first semiconductor material in the source and drain regions are less than or equal to the first percentage of the first semiconductor material in the bottom semiconductor layer.

### Claim 4 (depends on 1)

The finFET semiconductor device of claim 1, wherein the third and fourth percentages of the first semiconductor material in the source and drain regions are about equal to the first percentage of the first semiconductor material in the bottom semiconductor layer.

### Claim 5 (depends on 1)

The finFET semiconductor device of claim 1, wherein the bottom semiconductor layer comprises a thickness in a range of about 5 nm to about 15 nm and the channel fin comprises a thickness in a range of about 10 nm to about 75 nm.

### Claim 6 (depends on 5)

The finFET semiconductor device of claim 5, wherein the bottom semiconductor layer comprises a thickness of about 5 nm and the channel fin comprises a thickness of about 35 nm.

### Claim 7 (depends on 1)

The finFET semiconductor device of claim 1,
wherein a channel of the finFET semiconductor device comprises the channel fin and a first portion of the bottom semiconductor layer beneath the channel fin,
wherein a source of the finFET semiconductor device comprises the source region and a second portion of the bottom semiconductor layer beneath the source region, and
wherein a drain of the finFET semiconductor device comprises the drain region and a third portion of the bottom semiconductor layer beneath the drain region.

### Claim 8 (depends on 7)

The finFET semiconductor device of claim 7, further comprising a gate stack on a top surface of the channel fin and extending down sidewall surfaces of the channel fin.

### Claim 9 (depends on 8)

The finFET semiconductor device of claim 8, wherein the drain region is on a recessed portion of the bottom semiconductor layer, wherein a distance between adjacent surfaces of the drain region and the insulator layer is less than a distance between adjacent surfaces of the channel fin and the insulator layer.

### Claim 10 (depends on 9)

The finFET semiconductor device of claim 9,
wherein the first percentage of the first semiconductor material in the bottom semiconductor layer is in a range of about 10% to about 40%,
wherein the fourth percentage of the first semiconductor material in the drain region is in a range of about 10% to about 40% and less than or equal to the first percentage of the first semiconductor material in the bottom semiconductor layer, and
wherein the second percentage of the first semiconductor material in the channel fin is in a range of about 5% to about 35% and less than the fourth percentage of the first semiconductor material in the drain region.

### Claim 11 (depends on 1)

The finFET semiconductor device of claim 1,
wherein the finFET semiconductor device is an n-type finFET,
wherein the drain region comprises a lower drain region adjacent the bottom semiconductor layer and a upper drain region on the lower drain region, and
wherein the upper drain region comprises an upper drain percentage of the first semiconductor material in the upper drain region that is higher than a lower drain percentage of the first semiconductor material in the lower drain region.

### Claim 12 (depends on 1)

The finFET semiconductor device of claim 1,
wherein the finFET semiconductor device is a p-type finFET,
wherein the drain region comprises a lower drain region adjacent the bottom semiconductor layer and a upper drain region on the lower drain region, and
wherein the upper drain region comprises an upper drain percentage of the first semiconductor material in the upper drain region that is less than a lower drain percentage of the first semiconductor material in the lower drain region.

### Claim 13 (depends on 1)

The finFET semiconductor device of claim 1,
wherein the finFET semiconductor device is a p-type finFET,
wherein the drain region comprises an upper drain region adjacent the bottom semiconductor layer and a lower drain region on the lower drain region, and
wherein the upper drain region comprises:
silicon and germanium, wherein an upper drain percentage of the silicon in the upper drain region is less than a lower drain percentage of silicon in the lower drain region; and/or
germanium and tin, wherein a percentage of tin in the upper drain region is less than or equal to about 20%.

### Claim 14 (depends on 1)

The finFET semiconductor device of claim 1,
wherein the channel fin, source region, and drain region comprise a first channel fin, a first source region, and a first drain region, respectively, of an n-type finFET,
wherein the finFET semiconductor device further comprises a p-type finFET,
wherein the p-type finFET comprises a second channel fin, a second source region, and a second drain region, each on the bottom semiconductor layer, and
wherein percentages of the first semiconductor material in the second channel fin, the second source region, and the second drain region are about equal to the second, third, and fourth percentages, respectively, of the first semiconductor material.

### Claim 15 (depends on 1)

The finFET semiconductor device of claim 1,
wherein the channel fin, source region, and drain region comprise a first channel fin, a first source region, and a first drain region, respectively, of an n-type finFET,
wherein the finFET semiconductor device further comprises a p-type finFET,
wherein the p-type finFET comprises a second channel fin, a second source region, and a second drain region, each on the bottom semiconductor layer, and
wherein percentages of the first semiconductor material in the second channel fin, the second source region, and the second drain region are different from the second, third, and fourth percentages, respectively, of the first semiconductor material.

### Claim 16 (depends on 1)

The finFET semiconductor device of claim 1,
wherein the channel fin, source region, and drain region comprise a first channel fin, a first source region, and a first drain region, respectively, of an n-type finFET,
wherein the finFET semiconductor device further comprises a p-type finFET,
wherein the p-type finFET comprises a second channel fin, a second source region, and a second drain region, each on the bottom semiconductor layer, and
wherein at least one of percentages of the first semiconductor material in the second channel fin, the second source region, and the second drain region is different from the second, third, and fourth percentages, respectively, of the first semiconductor material.

### Claim 17 (depends on 16)

The finFET semiconductor device of claim 16,
wherein the different at least one of the percentages of the first semiconductor material in the second channel fin, the second source region, and the second drain region is a product of a masked Ge condensation process that decreases a percentage of silicon in the bottom semiconductor layer and/or the channel fin of the n-type finFET.

### Claim 18

A method of forming a finFET semiconductor device, comprising:
forming a donor wafer including a first substrate, a first layer including SiyGe1-y on the substrate, and a second layer including SixGe1-x, x>y, on the first layer;
forming a cleaving surface in the donor wafer between the substrate and at least a portion of the first layer;
forming an insulator layer on a second substrate;
bonding the donor wafer to the insulator layer with the second layer adjacent the insulator layer; and
cleaving the donor wafer at the cleaving surface.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
etching the first and second layers to form a fin;
forming a dummy gate on a channel portion of the fin between first and second exposed portions of the fin not covered by the dummy gate;
recessing the first and second exposed portions of the fin; and
forming a source region in the recessed first exposed portion and a drain region in the recessed second exposed portion, wherein the source and drain regions include SizGe1-z, and wherein z>y.

### Claim 20 (depends on 18)

The method of claim 18, wherein a thickness of the second layer is substantially less than a thickness of the first layer and a lattice constant of the second layer is substantially the same as a lattice constant of the first layer.