Method and apparatus for driving half bridge connected semiconductor power switches with a stable and extremely short interlock delay combined with a switching transition speed increase and a driving power consumption reduction

A driving circuit for at least one voltage controlled power switch device comprising:

• a driver signal generating circuit configured to receive a pulse width modulated signal and to generate logical pulse signals as:
• a first driver signal in response to a rising edge of said pulsed signal, wherein the first driver signal is generated as a logical pulse signal comprising logical pulses for the duration of a set-up time at every rising edge of the pulse width modulated signal;
• a second driver signal in response to a falling edge of said pulsed signal, wherein the second driver signal is generated as a logical pulse signal comprising logical pulses for the duration of the set-up time at every falling edge of the pulse width modulated signal;
• at least one trigger signal generating circuit, each trigger signal generating circuit configured to generate a trigger signal for said one voltage controlled power switch device, said at least one trigger signal generating circuit comprising:
• a first driving transistor configured to be switched on by the first driver signal such that an on-voltage of the trigger signal is supplied to a control electrode of said at least one voltage controlled power switch device, and
• a second driving transistor configured to be switched on by the second driver signal such that an off-voltage of the trigger signal is supplied to the control electrode of said at least one voltage controlled power switch device.

A driving circuit for driving half bridge connected electrically controlled power switches with a near zero interlock delay time between on-states of the power switches,

• wherein the driving circuit is configured to receive an input signal and to generate:
• a first drive signal being adapted to switch a first power switch between the on and off state,
• a second drive signal being adapted to switch a second power switch between the on and off state,
• wherein the signal curve of the first drive signal generated in response to a rising and falling edge of said input signal is mirrored with respect to the signal curve of the second drive signal along a time axis of a mirroring voltage value within a transition time,
• wherein the mirroring voltage value is adjusted such to be within the cutoff region of the power switches.

A method for driving half bridge connected electrically controlled power switches in terms of having a near zero interlock delay time between on-states of the power switches comprising the steps of:

• generating a first and a second triggering signal,
• wherein the first triggering signal changes as a response to every odd step change of an input signal its value in a step manner from an off-voltage state to a positive DC gate supply voltage simultaneously with the second triggering signal which changes its value in a step manner from an on-voltage state to a negative DC gate supply voltage end
• wherein the first triggering signal changes as a response to every even step change of an input signal its value in a step manner from an on-voltage state to a negative DC gate supply voltage simultaneously with the second triggering signal which changes its value in a step manner from an off-voltage state to a positive DC gate supply voltage,
• sloping said first and said second triggering signal to a first and a second drive signal with equal slopes as a response to the rising and falling edges of the input signal,
• wherein said first and second drive signal are adapted to switch a corresponding power switch among the on and off state,
• wherein said first and second drive signal are mirrored with respect to one another's time curve along the time axis through a mirroring voltage value within a transition time and wherein the said mirroring voltage value is adjusted to be low enough for said power switches to be within a cutoff region.