# US 2015/0104902 A1 · Method for fastening chips with a contact element onto a substrate provided with a functional layer having openings for the chip contact elements > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0104902 A1 - Document ID: US20150104902A1 - Status: Published application - Kind: A1 - Application number: 14/395,084 - Filed: 2013-03-18 - Published: 2015-04-16 - Earliest claimed: 2012-04-19 - Assignees: EV Group E. Thallner GmbH - Applicants: Ev Group E. Thallner GmbH - Inventors: Jurgen Burggraf; Markus Wimplinger; Harald Wiesbauer; Alfred Sigl - Web page: https://patentgrep.com/patent/US20150104902A1 ## CPC - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 72/01333: {in liquid form, e.g. spin coating, spray coating or immersion coating} - H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil} - H10W 72/01338: {in gaseous form, e.g. by CVD or PVD} - H10W 72/01355: {by use of masks} - H10W 72/01361: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01351)} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07231: {Techniques} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating} - H10W 72/07311: {Treating the bonding area before connecting, e.g. by applying flux or cleaning} - H10W 72/07331: {Connecting techniques} - H10W 72/07332: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/331: {Shapes of die-attach connectors} - H10W 72/332: {Plan-view shape, i.e. in top view} - H10W 72/354: {comprising polymers} - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate. The method includes the following steps: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements. ## Claims ### Claim 1 A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate said method comprising: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein the method further comprises: treating the function layer with a solvent on the chip contact side in order to induce an adhesion property which is necessary for tacking. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the method further comprises: providing the function layer with an adhesion layer on the chip contact side. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the step of removing the function layer from the substrate includes uncovering of an exposed area of the surface of the substrate located outside of the chip positions. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein the step of removing the function layer from the substrate includes formation of channels in the function layer. ### Claim 6 (depends on 1) The method as claimed in claim 1, wherein the function layer is comprised of a material having low elasticity. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein the uncovering of the contacts takes place by photostructuring. ### Claim 8 (depends on 1) The method as claimed in claim 1, wherein the method further comprises: forming through openings in the function layer when the contacts are uncovered, said openings extending as far as the contacts. ### Claim 9 The method as claimed in 1, wherein the method further comprises: aligning the chips with the contacts before tacking. ### Claim 10 (depends on 1) The method as claimed in claim 1, wherein the method further comprises: permanently bonding the chips to the function layer after tacking. ### Claim 11 (depends on 2) The method as claimed in claim 2, wherein the function layer is treated with the solvent on the chip contact side immediately before tacking. ### Claim 12 (depends on 4) The method as claimed in claim 4, wherein uncovering of the exposed area takes place by photostructuring. ### Claim 13 (depends on 12) The method as claimed in claim 12, wherein the photostructuring includes the following steps: exposure of the function layer on the areas which are to be uncovered, lithography of the areas which are to be uncovered, and stripping of the areas which are to be uncovered. ### Claim 14 (depends on 5) The method as claimed in claim 5, wherein formation of the channels takes place by photostructuring. ### Claim 15 (depends on 14) The method as claimed in claim 14, wherein the photostructuring includes the following steps: exposure of the function layer on the areas which are to be uncovered, lithography of the areas which are to be uncovered, and stripping of the areas which are to be uncovered. ### Claim 16 (depends on 5) The method as claimed in claim 5, wherein the channels are formed in the function layer beginning from the contacts. ### Claim 17 (depends on 5) The method as claimed in claim 5, wherein the channels are formed in the function layer ending on an exposed area of the surface of the substrate located outside of the chip positions. ### Claim 18 (depends on 7) The method as claimed in claim 7, wherein the photostructuring includes the following steps: exposure of the function layer on the areas which are to be uncovered, lithography of the areas which are to be uncovered, and stripping of the areas which are to be uncovered. ### Claim 19 (depends on 8) The method as claimed in claim 8, wherein said openings are arranged concentrically to the contacts. ### Claim 20 (depends on 8) The method as claimed in claim 8, wherein said openings have a diameter D1 greater than a diameter D2 of the contact elements.