# US 2015/0103069 A1 · Array substrate, 3d display device and driving method for the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2015/0103069 A1 - Document ID: US20150103069A1 - Status: Published application - Kind: A1 - Application number: 14/100,719 - Filed: 2013-12-09 - Published: 2015-04-16 - Earliest claimed: 2012-12-10 - Assignees: Beijing Boe Display Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Beijing Boe Display Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Liang ZHANG; Xibin SHAO; Dan WANG; Weihao HU; Yizhen XU; Shuai HOU - Web page: https://patentgrep.com/patent/US20150103069A1 ## CPC - G09G 3/003: {to produce spatial visual effects} - H04N 13/144: for flicker reduction - G09G 2310/0254: Control of polarity reversal in general, other than for liquid crystal displays - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract The present invention provides an array substrate, a 3D display device and a driving method for the same, and belongs to the field of 3D display. Wherein, the array substrate comprises: a substrate, and 2n rows of pixel units being arranged on the substrate in a matrix form, the array substrate further comprises gate lines corresponding to the pixel units in each row, and each of the gate lines is connected to the gate electrodes of thin film transistors in corresponding pixel units, wherein the gate line corresponding to pixel units in the (2k−1)th row of pixel units or the gate line corresponding to the 2kth row receives the gate scanning signal in a predetermined time period, wherein k is a natural number which is not less than 1 and not greater than n. ## Claims ### Claim 1 An array substrate, including: a substrate, and 2n rows of pixel units arranged on the substrate in a matrix form, the array substrate further comprises gate lines each of which corresponds to the pixel units in each row, and each of the gate lines is connected to the gate electrodes of thin film transistors in corresponding pixel units, wherein the gate line corresponding to pixel units in the (2k−1)th row or the gate line corresponding to pixel units in the 2kth row receives the gate scanning signal in a predetermined time period, wherein n is a natural number and k is a natural number which is not less than 1 and not greater than n. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein the gate lines corresponding to pixel units in the 1st row, the 3rd row, . . . , the (2k−1)th row, . . . , the (2n−1)th row receive the gate scanning signal sequentially in the predetermined time period; and the gate lines corresponding to pixel units in the 2nd row, the 4th row, . . . , the 2kth row, . . . , the 2nth row do not receive the gate scanning signal in the predetermined time period. ### Claim 3 (depends on 1) The array substrate according to claim 1, wherein the gate lines corresponding to pixel units in the 2nd row, the 4th row, . . . , the 2kth row, . . . , the 2nth row receive the gate scanning signal sequentially in the predetermined time period; and the gate lines corresponding to pixel units in the 1st row, the 3rd row, . . . , the (2k−1)th row, . . . , the (2n−1)th row do not receive the gate scanning signal in the predetermined time period. ### Claim 4 (depends on 1) The array substrate according to claim 1, wherein a time length of the predetermined time period is within a range of 1/480˜1/120 s. ### Claim 5 (depends on 1) A 3D display device, wherein the 3D display device comprises the array substrate according to claim 1 and a drive circuit, the drive circuit comprises: a gate driving circuit, configured to provide the gate scanning signal to the gate line corresponding to pixel units in the (2k−1)th row in the predetermined time period; or provide the gate scanning signal to the gate line corresponding to pixel units in the 2kth row in the predetermined time period. ### Claim 6 (depends on 5) The 3D display device according to claim 5, wherein the gate lines corresponding to pixel units in the 1st row, the 3rd row, . . . , the (2k−1)th row, . . . , the (2n−1)th row receive the gate scanning signal sequentially in the predetermined time period; and the gate lines corresponding to pixel units in the 2nd row, the 4th row, . . . , the 2kth row, . . . , the 2nth row do not receive the gate scanning signal in the predetermined time period. ### Claim 7 (depends on 5) The 3D display device according to claim 5, wherein the gate lines corresponding to pixel units in the 2nd row, the 4th row, . . . , the 2kth row, . . . , the 2nth row receive the gate scanning signal sequentially in the predetermined time period; and the gate lines corresponding to pixel units in the 1st row, the 3rd row, . . . , the (2k−1)th row, . . . , the (2n−1)th row do not receive the gate scanning signal in the predetermined time period. ### Claim 8 (depends on 5) The 3D display device according to claim 5, wherein a time length of the predetermined time period is within a range of 1/480˜1/120 s. ### Claim 9 (depends on 5) A method for driving the 3D display device according to claim 5, wherein the driving method comprises: transmitting the gate scanning signal to the gate line corresponding to pixel units in the (2k−1)th row in the predetermined time period; or transmitting the gate scanning signal to a gate line corresponding to pixel units in the 2kth row in the predetermined time period. ### Claim 10 (depends on 9) The method according to claim 9, wherein transmitting the gate scanning signal to the gate line corresponding to pixel units in the (2k−1)th row in the predetermined time period comprises: transmitting the gate scanning signal to the gate lines corresponding to pixel units in the 1st row, the 3rd row, . . . , the (2k−1)th row, . . . , the (2n−1)th row sequentially in the predetermined time period; not transmitting the gate scanning signal to the gate lines corresponding to pixel units in the 2nd row, the 4th row, . . . , the 2kth row, . . . , the 2nth row sequentially in the predetermined time period. ### Claim 11 (depends on 9) The method according to claim 9, wherein transmitting the gate scanning signal to the gate line corresponding to pixel units in the 2kth row in the predetermined time period comprises: transmitting the gate scanning signal to the gate lines corresponding to pixel units in the 2nd row, the 4th row, . . . , the 2kth row, . . . , the 2nth row sequentially in the predetermined time period; not transmitting the gate scanning signal to the gate lines corresponding to pixel units in the 1st row, the 3rd row, . . . , the (2k−1)th row, . . . , the (2n−1)th row sequentially in the predetermined time period. ### Claim 12 (depends on 9) The method according to claim 9, wherein a time length of the predetermined time period is within a range of 1/480˜1/120 s.