Circuit design support method, computer product, circuit design support apparatus, and semiconductor integrated circuit
AssigneeFujitsu Optical Components Limited
InventorTomoyasu Kitaura
Life of this patent
Estimating the term…
Abstract
A circuit design support method includes obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit; and calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires.
Claims22
A circuit design support method comprising:
- obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit;
- and
- calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires.
A non-transitory, computer-readable recording medium storing a circuit design support program that causes a computer to execute a process comprising:
- obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit;
- and
- calculating a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires.
A circuit design support apparatus comprising
- a processor configured to:
- obtain layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit;
- and
- calculate a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires.
A semiconductor integrated circuit comprising
- a plurality of partial areas, wherein
- each of the plurality of partial area includes:
- a plurality of clock receivers;
- a first clock wire;
- a second clock wire disposed in a direction perpendicular to a direction of the first clock wires;
- a plurality of leading wires that connect the plurality of clock receivers and the second clock wire;
- and
- a circuit to which a clock signal is supplied through at least one of the plurality clock receivers and a leading wire,
- in a first partial area among the plurality of partial areas, a count of the second clock wire is one and a wire width of the second clock wire is a reference wire width, and
- in a second partial area among the plurality of partial areas, the count of the second clock wire is “n” (where, n is an integer of two or more) and a wire width of each of the n second clock wires is different from the reference wire width.
Dependencies are inferred from the claim text.