Method and devices for time and frequency synchronization using a phase locked loop

A method of synchronizing the time and frequency of a slave clock in a slave device to a master clock in a master device which is connected to the slave device over a network, the method including the steps of:

• exchanging, between the master device and the slave device, timing messages and timestamps which are:
• the time of sending of timing messages from the master device according to the master clock;
• the time of receipt of said timing messages according to the slave clock;
• the time of sending of said timing messages according to the slave clock;
• and the time of receipt of said timing messages according to the master clock,
• estimating the skew and offset of the slave clock relative to the master clock from said timestamps;
• and
• synchronizing said slave clock to the master clock based on the estimated skew and offset to produce a master time estimate;
• using a digital phase locked loop including a phase detector, a loop filter, a phase accumulator and a counter, processing the master time estimate as follows:
• on receipt of a first estimate of the master time, initializing the counter;
• on receipt of subsequent estimates of the master time, detecting, using the phase detector, a phase difference between the output of the counter and the received estimate and producing an error signal representing that difference;
• filtering the error signal using the loop filter to produce a filtered error signal;
• controlling the frequency of the phase accumulator using the filtered error signal;
• and
• incrementing counter using the output of the phase accumulator, and
• obtaining a clock frequency of the slave clock which is synchronized to the frequency of the master clock as the output of the phase accumulator.

A time and frequency synchronisation system for a network, the system including:

• a master device having a master clock;
• a slave device having a slave clock;
• and
• a network connecting the master and slave devices, wherein:
• the slave clock comprises:
• a slave clock;
• and
• a digital phase locked loop including a phase detector, a loop filter, a phase accumulator and a counter, wherein:
• the slave device is arranged to:
• exchange with the master device, timing messages and to record timestamps which are:
• the time of sending of said timing messages from the master device according to the master clock;
• the time of receipt of said timing messages according to the slave clock;
• the time of sending of said timing messages according to the slave clock;
• and the time of receipt of said timing messages according to the master clock,
• estimate the skew and offset of the slave clock relative to the master clock from said timestamps;
• and
• synchronize said slave clock to the master clock based on the estimated skew and offset to produce a master time estimate;
• the digital phase locked loop processes the master time estimate as follows:
• on receipt of a first estimate of the master time, the counter is initialised;
• on receipt of subsequent estimates of the master time, the phase detector is arranged to detect a phase difference between the output of the counter and the received estimate and produce an error signal representing that difference;
• the error signal is filtered by the loop filter to produce a filtered error signal;
• the filtered error signal is used to control the frequency of the phase accumulator;
• and
• the output of the phase accumulator increments the counter and also provides a clock frequency of the slave clock which is synchronized to the frequency of the master clock.