Fault Tolerant Chip-to-Chip Communication with Advanced Voltage Regulator
AssigneeKandou Labs, S.A.
InventorsAmin Shokrollahi, Roger Ulrich
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Abstract
Systems and circuits are described for transmitting data over physical channels to provide a fault tolerant, high speed, low latency interface such as between a memory controller and memory devices. Communications signals are communicated over interconnection groups comprised of multiple wires, with the described encoding and decoding permitting continued communication in the presence of a wire failure within an interconnection group. An efficient distributable voltage regulator to provide communications driver power is also disclosed.
Claims11
A system for data communications over a multiple signal wire communications channel, the system comprising:
- a fault detector configured to identify at least one failed signal wire of the multiple signal wires;
- a transmitter configured in response to the detected fault to encode units of data using a vector signaling code and emit the encoded data as groups of signals carried by the communications channel;
- and,
- a receiver configured in response to the detected fault to decode the groups of signals carried by the communications channel to produce received units of data.
A circuit for data communications over a multiple signal wire communications channel, the circuit comprising:
- a fault detector configured to identify one or more failed signal wires of the multiple signal wires;
- a transmitter configured in response to the detected fault to direct vector signaling code encoded data to selected wires of the multiple signal wires of the communications channel;
- and,
- a receiver configured in response to the detected fault to detect vector signal code encoded data from selected wires of the communications channel and decode receive data.
Dependencies are inferred from the claim text.