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US 2015/0092499 A1Published application
Slew rate modulation
AssigneeMicron Technology, Inc.
InventorDaesik Song
Life of this patent
Estimating the term…
Abstract
Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.
Claims20
A memory, comprising:
- a plurality of memory cells;
- and
- an input/output circuit coupled to the plurality of memory cells, and configured to drive data from at least one of the plurality of memory cells onto a data node, the input/output circuit comprising:
- a plurality of pull-up transistors coupled between a first node and the data node;
- a plurality of pull-up circuits configured to receive a data signal, each of the plurality of pull-up circuits including a transistor configured to provide the data signal to a latch responsive to a respective timing signal and wherein each pull-up circuit of the plurality of pull-up circuits is further configured to provide a respective control signal from the latch to a gate of a respective pull-up transistor of the plurality of pull-up transistors responsive to the data signal and the respective timing signal, wherein the respective pull-up transistor is configured to switch responsive to the respective control signal;
- and
- a plurality of timing circuits coupled to the plurality of pull-up circuits, each of the plurality of timing circuits configured to provide the respective timing signal to a respective one of the plurality of pull-up circuits, and wherein the plurality of timing circuits are configured to provide the timing signals to cause the plurality of pull-up circuits to provide the respective control signals to switch the pull-up transistors at different times to modulate a slew rate of a signal on the data node.
4 more elements
A memory comprising:
- a plurality of memory cells;
- a driver circuit coupled to the plurality of memory cells, the driver circuit configured to drive data from the plurality of memory cells onto a data node based at least in part on a control signal, the driver circuit comprising:
- a plurality of pull-up transistors coupled between a first node and the data node;
- and
- a plurality of pull-up circuits configured to receive a data signal, each of the plurality of pull-up circuits is configured to provide the data signal to a latch responsive to a respective timing signal and wherein each of the plurality of pull-up circuits is further configured to provide a respective control signal to a gate of a respective pull-up transistor of the plurality of pull-up transistors responsive to the data signal and the respective timing signal, wherein the respective pull-up transistor of the plurality of pull-up transistors is configured to switch responsive to the respective control signal;
- and
- a plurality of timing circuits coupled to the plurality of pull-up circuits, each one of the plurality of timing circuits configured to provide the respective timing signal to a respective one of the plurality of pull-up circuits, and wherein each of the plurality of timing circuits is configured to provide the respective timing signals to cause the plurality of pull-up circuits to provide the control signals to switch the pull-up transistors at different times to modulate a slew rate of a signal on the data node.
4 more elements
A system, comprising:
- a processor;
- and
- a memory coupled to the processor, the memory comprising:
- a plurality of memory cells;
- and
- a driver circuit coupled to the plurality of memory cells, the driver circuit configured to drive data from at least one of the plurality of memory cells onto the data node, the driver circuit comprising:
- a plurality of pull-up transistors coupled between a first node and the data node;
- a plurality of pull-up circuits configured to receive a data signal, each of the plurality of pull-up circuits is configured to latch the data signal responsive to a respective timing signal and wherein each of the plurality of pull-up circuits is further configured to provide a respective control signal to a gate of a respective pull-up transistor of the plurality of pull-up transistors responsive to the data signal, an output enable signal, and the respective timing signal, wherein the respective pull-up transistor of the plurality of pull-up transistors is configured to switch responsive to the respective control signal;
- and
- a plurality of timing circuits coupled to the plurality of pull-up circuits, each of the plurality of timing circuits configured to provide the respective timing signal to a respective one of the pull-up circuits responsive to a clock signal, and wherein each of the plurality of timing circuits is configured to provide the respective timing signals to cause the plurality of pull-up circuits to provide the control signals to switch the pull-up transistors at different times to modulate a slew rate of a signal on the data node.
7 more elements
The system of 15, wherein the control logic is configured to provide a bypass signal to each of the plurality of timing circuits to disable slew rate modulation.
Dependencies are inferred from the claim text.