Semiconductor memory device and erasing method
AssigneeWinbond Electronics Corp.
InventorMakoto Senoo
Life of this patent
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Abstract
A reliable semiconductor memory device and an erasing method for erasing data in a reliable manner are provided. The erasing method is applied to erase a semiconductor memory device having a memory array, and the memory array has an NAND string. A predetermined voltage is applied to a gate of a select transistor of the NAND string, and the predetermined voltage is applied to a word line of a memory cell of the NAND string. An erasing voltage is applied to a substrate region at a first timing, and the substrate region has the NAND string. The gate of the select transistor is floated at a second timing. Here, there is a fixed time interval between the first timing and the second timing, and the second timing is later than the first timing.
Claims10
An erasing method for erasing a semiconductor memory device having a memory array, the memory array having an NAND string, the erasing method comprising:
- applying a predetermined electrical potential to a gate of a select transistor of the NAND string and applying the predetermined electrical potential to a word line of a memory cell of the NAND string;
- applying an erasing voltage to a substrate region having the NAND string at a first timing;
- and
- floating the gate of the select transistor at a second timing, wherein a fixed time interval is between the first timing and the second timing, and the second timing is later than the first timing.
A semiconductor memory device comprising:
- a memory array having an NAND string, the NAND string comprising a plurality of memory cells serially connected together, the memory cells on one side being connected to a first select transistor of a bit line, the memory cells on the other side being connected to a second select transistor of a source line;
- and
- an erasing device selecting a block from the memory array and erasing data from the memory cells in the selected block,
- wherein after a predetermined voltage was applied to word lines of the memory cells and select gate lines of the first and second select transistors in the selected block, the erasing device applies an erasing voltage to a substrate region in the selected block at a first timing, and floats the select gate lines of the first and second select transistors at a second timing, a fixed time interval is between the first timing and a second timing, and the second timing is later than the first timing.
Dependencies are inferred from the claim text.