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US 2015/0092486 A1Published application
Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
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Abstract
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
Claims20
1-19. (canceled)
A multi-port semiconductor memory cell comprising:
- a plurality of gates;
- a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell;
- and
- a plurality of conductive regions of a second conductivity type,
- wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;
- wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal;
- and
- wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.
5 more elements
A semiconductor memory cell comprising:
- a plurality of bipolar devices;
- and
- a common base region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell;
- wherein adjacent ones of each of said bipolar devices are separated by a conductive region having a second conductivity type;
- wherein said common base region is shared among said plurality of bipolar devices;
- and
- wherein one of said plurality of bipolar devices is configured to maintain the charge stored in said common base region.
4 more elements
A semiconductor memory cell comprising:
- a substrate region;
- a plurality of gates;
- a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell;
- a plurality of conductive regions of a second conductivity type,
- wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;
- and
- an insulator layer located beneath said common body region insulating said common body region from the substrate;
- wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal;
- and
- wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.
7 more elements
Dependencies are inferred from the claim text.