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US 2015/0092479 A1Published application
Resistance-based memory cells with multiple source lines
AssigneeQUALCOMM Incorporated
InventorXiangyu Dong
Life of this patent
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Abstract
In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
Claims26
A device comprising:
- a resistance-based memory cell having multiple access transistors, wherein a coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
A device comprising:
- a word line controller;
- and
- a row of resistance-based memory cells coupled to the word line controller, wherein a resistance-based memory cell in the row of the resistance-based memory cells comprises multiple access transistors, wherein a coupling configuration of the multiple access transistors to multiple source lines encodes a first data value.
A method for reading data, the method comprising:
- biasing at least one of a first source line and a second source line relative to a bit line, wherein the first source line and the bit line are coupled to a resistance-based memory cell;
- activating a first access transistor of the resistance-based memory cell;
- and
- detecting a data value based on whether the first access transistor enables a read current to flow through the resistance-based memory cell.
1 more element
A device comprising:
- means for biasing at least one of a first source line and a second source line relative to a bit line;
- means for activating a first access transistor of a resistance-based memory cell, wherein the resistance-based memory cell is coupled to the first source line and to the bit line;
- and
- means for detecting a data value based on whether the first access transistor enables a read current to flow through the resistance-based memory cell.
1 more element
A computer readable storage device storing instructions that are executable by a processor to perform operations comprising:
- biasing at least one of a first source line and a second source line relative to a bit line;
- activating a first access transistor of a resistance-based memory cell, wherein the resistance-based memory cell is coupled to the first source line and to the bit line;
- and
- detecting a data value of the resistance-based memory cell based on whether the first access transistor enables a read current to flow through the resistance-based memory cell.
1 more element
A method comprising:
- a first step for biasing at least one of a first source line and a second source line relative to a bit line wherein a resistance-based memory cell is coupled to the first source line, to the second source line, and to the bit line;
- a second step for activating a first access transistor of the resistance-based memory cell;
- and
- a third step for detecting a data value based on whether the first access transistor enables a read current to flow through the resistance-based memory cell.
1 more element
A method comprising:
- receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising a resistance-based memory cell having multiple access transistors, wherein a coupling configuration of the multiple access transistors to multiple source lines encodes a data value;
- and
- transforming the design information to generate a data file.
Dependencies are inferred from the claim text.