Adaptive data-retention-voltage regulating system for sram

An adaptive data-retention-voltage regulating system for static random-access memory (SRAM) comprising:

• a power supply unit having a primary power transistor and a secondary power transistor connected to each other while the size of the secondary power transistor is no more than the size of the primary power transistor;
• the power supply unit used for voltage supply of the SRAM:
• a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of the SRAM and having a DRV monitor circuit mounted with a plurality of memory cells of the SRAM, a reset signal generating circuit for resetting the DRV monitor circuit, and an adaptive variation control circuit that generates noise bias according to leakage current for adjusting reaction speed of the DRV monitor circuit;
• a first node of each of the memory cells are connected to one another and a second node of each of the memory cells are connected to one another;
• a data loss detector connected to the first node and the second node respectively and generating a data loss signal when voltage of the first node and voltage of the second node reverse;
• and
• a dynamic regulating controller that receives the data loss signal for generating a refresh signal and a switch signal that are sent to the reset signal generating circuit and the secondary power transistor respectively.