Resistive memory device, method of fabricating the same, and memory apparatus and data processing system having the same
AssigneeSK hynix Inc.
InventorSung Min LEE
Life of this patent
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Abstract
A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.
Claims16
1-11. (canceled)
A resistive memory apparatus, comprising:
- a memory cell array including a plurality of memory cells connected between word lines and bit lines;
- and
- a controller configured to control data write and data read for a selected memory cell in the memory cell array,
- wherein each of the plurality of memory cells includes a resistive device and a selection device,
- wherein the resistive device includes:
- a lower electrode;
- a first phase-change material layer formed over the lower electrode;
- a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer;
- and
- an upper electrode formed over the first phase-change material layer and the second phase-change material layer.
A data processing system, comprising:
- a resistive memory apparatus which includes a memory cell array including a plurality of memory cells connected to bit lines and word lines, each of memory cells including a resistive device and a selection device, and a controller configured to control an operation of the memory cell array;
- and
- a memory controller configured to access the resistive memory apparatus in response to request of a host,
- wherein the resistive device includes:
- a lower electrode;
- a first phase-change material layer formed over the lower electrode;
- a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer;
- and
- an upper electrode formed over the first phase-change material layer and the second phase-change material layer.
A data processing system, comprising:
- a processor;
- an operation memory configured to store an application, data, and a control signal required for an operation of the processor;
- a resistive memory apparatus which is accessed by the processor and includes a memory cell array including a plurality of memory cells connected to bit lines and word lines, each of memory cells including a resistive device and a selection device;
- and
- a user interface configured to perform data input/output (I/O) between the processor and a user,
- wherein the resistive device includes:
- a lower electrode;
- a first phase-change material layer formed over the lower electrode;
- a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer;
- and
- an upper electrode formed over the first phase-change material layer and the second phase-change material layer.
Dependencies are inferred from the claim text.