Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array including a plurality of first lines disposed on a substrate, a plurality of second lines disposed intersecting the first lines, and memory cells disposed at each of intersections of the first lines and the second lines and each configured having a current rectifier element and a variable resistance element connected in series therein;
• and
• a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively, such that a first potential difference is applied to a selected memory cell in an operation on the selected memory cell disposed at the intersection of the selected first line and the selected second line,
• the control circuit being configured to apply a fifth voltage different to the third voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage different to the fourth voltage to one of the non-selected second lines that is adjacent to the selected second line.