Memory cells breakdown protection

A circuit comprising:

• a row of memory cells each comprising:
• a resistive random access memory (RRAM) device comprising a first electrode and a second electrode;
• and
• an access transistor comprising a gate to receive a first voltage during a reset operation, a first/source drain electrically connected to the first electrode of the RRAM device and a second source/drain;
• a voltage divider configured to generate an inhibition voltage according to an operation voltage and apply the inhibition voltage to at least one of a second electrode of the RRAM device and a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.