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US 2015/0092467 A1Published application
Driver Circuit for a Pair of Semiconductor Switches in a Leg of a Three-Level Inverter Half-Bridge
OwnerRaghavan Nagarajaninventor
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Abstract
A three-level driver circuit for an inverter half-bridge includes an output inverter half-bridge, which has four switches in series. The switches are controlled by signals from a switch controller applied via gate drivers. Switch delay times are taken into consideration to prevent short-circuiting when dimensioning the switching constellations of the switches.
Claims21
A driver circuit for a pair of switches in a leg of a three-level inverter half-bridge, comprising:
- a driver input configured to receive a two-level input signal that comprises at least one given pulse with a given pulse duration during which the input signal takes on one of the two levels;
- a first driver output configured to provide a control signal for one switch of the pair of switches;
- a second driver output configured to provide a control signal for the other switch of the pair of switches;
- a signal processing circuit that has one input branch, and first and second output branches in which:
- the input branch is coupled with the driver input, the first output branch is coupled with the first driver output and the second output branch is coupled with the second driver output;
- the first output branch is configured to provide a two-level output signal that comprises a first pulse with a first pulse duration during which the input signal takes on one of the two levels;
- the second output branch is configured to provide a two-level output signal that comprises a second pulse with a second pulse duration during which the second output signal takes on one of the two levels;
- the first length is smaller than or equal to the given length and the second length is smaller than the first length;
- and
- the second pulse occurs during the occurrence of the first pulse.
7 more elements
A three-level inverter half-bridge comprising a pair of transistors in each half-bridge leg and two driver circuits connected to the control inputs of the pair of transistors, wherein:
- each pair of transistors comprises a series connection of the load paths of an inner switch connected to an inverter output and an outer switch connected to an inverter supply line;
- and
- each of the driver circuits comprises:
- a driver input configured to receive a two-level input signal that comprises at least one given pulse with a given pulse duration during which the input signal takes on one of the two levels;
- a first driver output configured to provide a control signal for the outer switch of the pair of switches;
- a second driver output configured to provide a control signal for the inner switch of the pair of switches;
- a signal processing circuit that has one input branch, and first and second output branches, wherein:
- the input branch is coupled with the driver input, the first output branch is coupled with the first driver output and the second output branch is coupled with the second driver output;
- the first output branch is configured to provide a two-level output signal that comprises a first pulse with a first pulse duration during which the input signal takes on one of the two levels;
- the second output branch is configured to provide a two-level output signal that comprises a second pulse of a second pulse duration during which the second output signal takes on one of the two levels;
- the first length is smaller than or equal to the given length and the second length is smaller than the first length;
- and
- the second pulse occurs during the occurrence of the first pulse.
10 more elements
Dependencies are inferred from the claim text.