On Chip Reverse Polarity Protection Compliant with ISO and ESD Requirements

A semiconductor device comprising:

• a semiconductor chip including a substrate;
• a ground terminal configured to be provided with a reference potential;
• a supply terminal electrically coupled to the substrate, the supply terminal configured to be provided with a load current and configured to be provided with a supply voltage between the substrate and the ground terminal;
• an overvoltage protection circuit disposed in the semiconductor chip and coupled between the supply terminal and the ground terminal, the overvoltage protection circuit comprising:
• a first transistor having a load current path coupled between the supply terminal and an internal ground node;
• and
• a second transistor having a load current path coupled between the internal ground node and the ground terminal,
• wherein the second transistor is configured to be switched on when the supply voltage is positive, and the first transistor is configured to be switched on when the supply voltage is negative,
• wherein the first transistor is configured to be switched off when the supply voltage is positive but below a pre-defined maximum voltage, and the second transistor is configured to be switched off when the supply voltage is negative but above a pre-defined minimum voltage, and
• wherein the first transistor configured to be switched on when the supply voltage is positive and exceeds the pre-defined maximum voltage, and the second transistor is configured to be switched on when the supply voltage is negative and below the pre-defined minimum voltage.