Graphic processor unit and method of operating the same

A graphic processor unit, comprising:

• an instruction memory storing compiled source code from a host as an instruction;
• a scheduler decoding an instruction from the instruction memory, the scheduler being connected to a thread pool that stores a plurality of threads temporarily;
• a load/store unit calculating a base address designating a first row of a plurality of rows of a memory based on a multiple load instruction, when the decoded instruction from the scheduler is the multiple load instruction that instructs at load/store unit to load data stored in the plurality of rows of the memory;
• and
• a register file including at least one register to which the data stored in the memory are loaded based on the base address,
• wherein the multiple load instruction comprises second and third instructions,
• wherein the second instruction instructs the load/store unit to write control information in a control register of the at least one register of the register file and the control information includes at least mask bits designating selected rows of the memory that store data to be loaded from the plurality of rows of the memory to the at least one register of the register file, a span field representing a relationship of the plurality of rows of the memory to each other and a stride field, and
• wherein the third instruction instructs the load/store unit to store the data sequentially from a row of the memory corresponding to an address written in a base register of the at least one register of the register file to a first register of the at least one register of the register file as a starting register, according to the control information.

A graphic processor unit, comprising:

• a scheduler receiving and decoding a multiple load instruction;
• a load/store unit receiving the decoded multiple load instruction from the scheduler;
• and
• a register file comprising at least one register to which data stored in a memory are loaded based on a base address,
• wherein the multiple load instruction instructs the load/store unit to load data stored in a plurality of rows of the memory to the at least one register of the register file,
• wherein the multiple load instruction comprises first, second and third instructions,
• wherein the first instruction instructs the load/store unit to write the base address designating a first row of the plurality of rows of the system memory to a base register of the at least one register of the register file,
• wherein the second instruction instructs the load/store unit to write control information in a control register of the at least one register of the register file, the control information including at least mask bits designating selected rows of the memory that store data to be loaded from the plurality of rows of the memory to the at least one register of the register file, a span field representing a relationship of the plurality of rows of the memory to each other and a stride field, and
• wherein the third instruction instructs the load/store unit to store the data sequentially from a row of the memory corresponding to an address written in the base register of the at least one register of the register file to a first register of the at least one register of the register file as a starting register, according to the control information.