System on chip including configurable image processing pipeline and system including the same

A system on chip (SoC) comprising:

• a bus;
• a first image processing module switchably connected to the bus and configured to process received image data;
• a first image processing stage configured to transmit either
• first image data
• or second image data received from the bus
• as the received image data to at least one of
• the bus and
• the first image processing module
• through one of
• a first bypass path and
• a first scaler path
• in response to first control signals;
• and
• a second image processing stage configured to transmit either
• third image data received from the first image processing module or
• fourth image data received from the bus
• to the bus in response to second control signals.

An image processing system for processing image data from a plurality of image data sources, the system comprising:

• an application processor configured to control the image data sources,
• wherein the application processor comprises:
• a bus;
• a first image processing module switchably connected to the bus and configured
• to process received image data;
• a first image processing stage configured to transmit either
• first image data output from one of the image data sources
• or second image data received from the bus
• as the received image data to at least one of
• the bus and
• the first image processing module
• in response to first control signals;
• and
• a second image processing stage configured to transmit either
• third image data received from the first image processing module or
• fourth image data received from the bus
• to the bus through one of
• a second bypass path and
• a second scaler path
• in response to second control signals.