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US 2015/0091744 A1Published application
ACCURACY ENHANCEMENT TECHNIQUES FOR ADCs
AssigneeAnalog Devices, Inc.
InventorsJunhua SHEN, Ronald A. KAPUSTA
Life of this patent
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Abstract
Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.
Claims27
A method, comprising:
- performing bit trials, using a SAR ADC including a comparator, to convert an analog input signal into a digital output signal;
- after completing the bit trials, measuring a residue voltage at an input of the comparator;
- and
- adjusting the digital output signal based on the measured residue error value.
1 more element
A method, comprising:
- performing regular bit trials using a SAR ADC to convert an analog input signal into a digital output signal from a most significant bit (MSB) to a predetermined less significant bit of the ADC;
- after the predetermined less significant bit trial, performing extra bit trials at an equal and/or lower magnitude than the predetermined less significant bit trial;
- and
- combining the results of the regular bit trials and extra bit trials based on their corresponding bit weights to generate the digital output signal.
1 more element
A method, comprising:
- performing regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word;
- performing extra bit trials;
- combining results of the regular and extra bit trials to generate a digital output signal;
- measuring a residue error;
- and
- adjusting the digital output signal based on the measured residue error.
3 more elements
A circuit, comprising:
- a digital-to-analog (DAC) including a plurality of weighted components for performing bit trials;
- a comparator coupled to the DAC for performing the bit trials;
- and a
- successive approximation register (SAR) logic to control the bit trials,
- wherein the comparator is configured to perform a number of comparisons with residue error inputs after completion of the bit trials.
2 more elements
Dependencies are inferred from the claim text.