Injection locked oscillator
AssigneePanasonic Corporation
InventorsTakahiro Shima, Hiroshi Komori, Takeaki Watanabe
Life of this patent
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Abstract
An injection locked frequency divider includes a ring oscillator, an input terminal, an output terminal and a control voltage terminal. The ring oscillator has a three-stage cascade connection of a first amplification circuit including an N-channel MOS type transistor and P-channel MOS type transistors, a second amplification circuit configured in the same manner as the first amplification circuit and a third amplification circuit configured likewise. A high frequency signal is input to a gate terminal of each P-channel MOS type transistor. A predetermined DC control voltage is supplied to a gate terminal of each P-channel MOS type transistor.
Claims6
An injection locked oscillator comprising:
- a ring oscillator including a cascade connection of (2n+1) stages (n is an integer of 1 or more) of amplification circuits each having an N-channel MOS type transistor, a first P-channel MOS type transistor and a second P-channel MOS type transistor,
- wherein a high frequency signal is input to a gate terminal of the first P-channel MOS type transistor in each of the (2n+1) amplification circuits;
- and
- wherein a predetermined DC control voltage is supplied to a gate terminal of the second P-channel MOS type transistor in each of the (2n+1) amplification circuits.
An injection locked oscillator comprising:
- a ring oscillator including a cascade connection of (2n+1) stages (n is an integer of 1 or more) of amplification circuits each having an N-channel MOS type transistor and a P-channel MOS type transistor;
- a first N-channel MOS type transistor which is connected to the N-channel MOS type transistor in each of the (2n+1) amplification circuits;
- and
- a second N-channel MOS type transistor which is connected to the N-channel MOS type transistor in each of the (2n+1) amplification circuits;
- wherein a high frequency signal is input to a gate terminal of the first N-channel MOS type transistor;
- and
- wherein a predetermined DC control voltage is supplied to a gate terminal of the second N-channel MOS type transistor.
Dependencies are inferred from the claim text.