Variability resistant circuit element and signal processing method
AssigneeNXP B.V.
InventorsVibhu Sharma, Jose de Jesus Pineda De Gyvez
Life of this patent
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Abstract
A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.
Claims15
A sequential circuit arrangement, comprising:
- a latch element clocked by a clock input signal;
- a first logic gate arrangement for comparing a latch input signal and a latched version of the input signal to derive a difference signal;
- a second logic gate arrangement for deriving an error signal from the difference signal and a delayed version of the difference signal;
- a selection unit for selecting the latch element output or an inverted version of the latch element output in dependence on the error signal.
A method of processing an input signal within a sequential circuit arrangement, the method comprising:
- latching the input signal timed with a clock input signal;
- comparing the input signal and the latched version of the input signal to derive a difference signal;
- generating a delayed version of the difference signal;
- deriving an error signal from the difference signal and the delayed version of the difference signal;
- selecting the latch element output or an inverted version of the latch element output in dependence on the error signal.
Dependencies are inferred from the claim text.