State retention power gated cell

A standard cell for an integrated circuit, wherein the standard cell is arranged in two or more rows, the standard cell comprising:

• an active layer including wells having a first conductivity type, including a first well located in a first row and a second well located in a second, different row;
• a plurality of semiconductor devices formed in and on the active layer and arranged in the two or more rows, wherein the plurality of semiconductor devices includes at least one first semiconductor device formed partly in the first well and at least one second semiconductor device formed partly in the second well;
• a first power supply line only for the first row, wherein a current terminal of the first semiconductor device is coupled to the first power supply line;
• and
• a second power supply line for at least the second row, wherein a current terminal of the second semiconductor device is coupled to the second power supply line;
• wherein the first well is powered with a first bias voltage in a first operation mode and in a second, different operation mode, and the second well is powered with a second, different bias voltage in the first operation mode;
• wherein the first power supply line is powered with a first power voltage in both of the first and second operation modes;
• and
• wherein the second power supply line is powered with a second power voltage, which is different from the first power voltage, in the first operation mode, and powered down in the second operation mode.