High speed, low power, isolated buffer
AssigneeIntegrated Device Technology, Inc.
InventorChengming He
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.
Claims20
A BiCMOS buffer comprising:
- an input circuit that receives a signal;
- a selection circuit that enables and disables the input circuit to provide the signal to a buffer output;
- and
- an input disabling circuit that additionally disables the input circuit also disabled by the selection circuit.
A device comprising a buffer, the buffer comprising:
- an input circuit that receives a signal;
- a selection circuit that enables and disables the input circuit to provide the signal to a buffer output;
- and
- an input disabling circuit that additionally disables the input circuit that is also disabled by the selection circuit.
A method of operating a buffer comprising an input circuit, a selection circuit and an input disabling circuit, the method comprising:
- enabling the input circuit, by the selection circuit, to provide a signal received by the input circuit to a buffer output;
- disabling the input circuit, by the selection circuit;
- and
- additionally disabling the input circuit, by the input disabling circuit.
Dependencies are inferred from the claim text.