Clock multiplexing and repeater network
AssigneeCavium, Inc.
InventorsScott Meninger, Rohan Arora
Life of this patent
Estimating the term…
Abstract
A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies. Accordingly, the on-chip reference clocks are generated to provide the required reference clocks to each of the PMAs.
Claims25
An integrated circuit comprising:
- a clock generator connected to at least one clock line external to the integrated circuit, the clock generator being configured to receive at least one external clock signal at the at least one clock line and transmit a plurality of reference clock signals across a bus at the integrated circuit;
- a plurality of physical medium attachments (PMAs) configured to interface with a respective input and output channel external to the integrated circuit;
- a plurality of multiplexers connected to the bus, the plurality of multiplexers each configured to select among at least a subset of the plurality of reference clock signals to forward to at least one of the plurality of PMAs;
- and
- a plurality of repeaters connected to buffer one of the plurality of reference clock signals to be forwarded to at least one of the plurality of multiplexers.
A method of providing reference clocks at an integrated circuit, comprising:
- receiving, at the integrated circuit, at least one clock signal from a clock line external to the integrated circuit;
- transmitting, at the integrated circuit, a plurality of reference clock signals across a bus, the plurality of reference clock signals being based on the at least one external clock signal;
- selecting among at least a subset of the plurality of reference clock signals to forward to at least one of a plurality of physical medium attachments (PMAs) at the integrated circuit, the plurality of PMAs being configured to interface with a respective input and output channel external to the integrated circuit;
- and
- buffering at least one of the plurality of reference clock signals to be forwarded to the plurality of PMAs.
An integrated circuit comprising:
- a clock bus;
- a clock generator connected to at least one clock line external to the integrated circuit, the clock generator being configured to receive an external clock signal at the at least one clock line and generate, from the external clock signal, a plurality of reference clock signals having frequencies distinct from that of the external clock signal, the clock generator transmitting the plurality of reference clock signals across the clock bus;
- a plurality of multiplexers connected to the bus and at least one respective physical medium attachment (PMA), the plurality of multiplexers each configured to select among at least a subset of the plurality of reference clock signals to forward to the at least one respective PMA;
- and
- a plurality of repeaters connected to buffer one of the plurality of reference clock signals to be forwarded to at least one of the plurality of multiplexers via the clock bus.
Dependencies are inferred from the claim text.