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US 2015/0091620 A1Published application
Reducing current variation when switching clocks
AssigneeLSI Corporation
InventorSteven J. Pollock
Life of this patent
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Abstract
An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.
Claims14
An apparatus comprising:
- a glitchless divider configured to generate a first system clock in response to a divider value and a clock signal received from a first source, wherein said divider value changes from a first value to a second value in a predetermined number of steps;
- and
- a glitchless multiplexer configured to select between said first system clock and a second system clock in response to a control signal.
A method of switching clocks in an electronic circuit comprising:
- selecting between a first system clock having a first frequency and a second system clock having a second frequency in response to a control signal;
- generating an intermediate clock in response to a divider value and said first system clock;
- and
- changing said divider value from a first value to a second value in a predetermined number of steps to change a frequency of said intermediate clock between said first frequency and said second frequency.
1 more element
Dependencies are inferred from the claim text.