Embedded Non-volatile Memory Circuit for Implementing Logic Functions Across Periods of Power Disruption
AssigneeRadiant Technologies, Inc.
InventorJoseph T. Evans
Life of this patent
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Abstract
A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.
Claims9
A circuit comprising:
- a plurality of AMLs embedded in logic circuitry;
- first and second power terminals, said circuit being powered by a potential applied between said first and second power terminals;
- and
- a power monitoring circuit that monitors said potential between said first and second power terminals, said power monitoring circuit disconnecting said AMLs from circuit components connected thereto when said potential is less than a predetermined value.
Dependencies are inferred from the claim text.