US 2015/0091601 A1 · ON CHIP BIAS TEMPERATURE INSTABILITY CHARACTERIZATION OF A SEMICONDUCTOR DEVICE

Abstract

Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

Claims20

Dependent claims

A circuit comprising:

a transistor having a gate, drain, source, and body terminal;
two AC pad sets, wherein each pad set includes a plurality of conductive pads;
two DC pads configured to be in communication with a DC power supply and/or meter;
and wherein:
the gate terminal is configured to be in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets;
the drain terminal is configured to be in communication with a second conductive pad of an AC pad set;
the source terminal is configured to be in communication with a second conductive pad of another AC pad set;
and
one DC pad is in communication with the gate terminal through a first serial resistor and another DC pad is in communication with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

6 more elements

A method for stress testing a transistor formed in a semiconductor wafer, the method comprising:

providing, in said semiconductor wafer, two AC pad sets each having a plurality of AC pads each and one DC pad set having a plurality of DC pads that are formed in the semiconductor wafer and are in communication with structures of the transistor;
providing a plurality of switches that are in communication with pads included in the two AC pad sets;
configuring a first select plurality of switches of the plurality of switches for enabling application of a predetermined stress signal to a pad included in the plurality of AC pads;
removing the application of the predetermined stress signal;
configuring a second select plurality of switches of the plurality of switches for enabling characterization of a scattering parameter associated with the transistor;
and
configuring a third select plurality of switches of the plurality of switches for enabling DC characterization of the transistor.

4 more elements

A computer system to stress test a transistor formed in a semiconductor wafer, the computer system comprising:

one or more computer processors;
one or more computer-readable storage media;
program instructions stored on the computer-readable storage media for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to
provide, in said semiconductor wafer, a connection between the transistor and two AC pad sets each having a plurality of AC pads each;
provide a connection between the transistor and one DC pad set having a plurality of DC pads;
provide a connection a plurality of switches that are in communication with pads included in the two AC pad sets;
configure a first select plurality of switches for enabling application of a predetermined stress signal to a pad included in the plurality of AC pads for a predetermined time period;
remove the application of the predetermined stress signal;
configure a second select plurality of switches of the plurality of switches for enabling the one or more processors to execute program instructions to characterize a scattering parameter associated with the transistor;
and
configure a third select plurality of switches of the plurality of switches for enabling the one or more processors to execute program instructions to DC characterize the transistor.

9 more elements

Dependencies are inferred from the claim text.

On chip bias temperature instability characterization of a semiconductor device

Life of this patent

On chip bias temperature instability characterization of a semiconductor device

Life of this patent

Abstract

Claims20