Timer based pfm exit control method for a boost regulator

A control circuit in a boost switching regulator, the boost switching regulator being configured to receive an input voltage on a first terminal of an inductor and to generate a regulated output voltage on an output terminal for driving a load, the boost switching regulator comprising a main power switch coupled between a second terminal of the inductor and ground, a synchronous rectifier coupled between the second terminal of the inductor and the output terminal, and an output capacitor coupled to the output terminal and ground, the control circuit being configured to control the main power switch and the synchronous rectifier using a Pulse Frequency Modulation (PFM) feedback control loop for light load conditions and using a Pulse Width Modulation (PWM) feedback control loop for heavy load conditions, the regulated output voltage being fed back to the boost switching regulator as a feedback voltage on a feedback node of the feedback control loop, the control circuit comprising:

• a timer based PFM exit control circuit configured to receive a first control signal for controlling the main power switch, a zero-cross signal indicative of an inductor current flowing through the inductor having reached a zero current value, and a timer reference signal, the timer reference signal being indicative of a timer threshold duration, the timer based PFM exit control circuit assessing an idle time of the inductor current based on the first control signal and the zero-cross signal, the idle time being the time period when the inductor current has the zero current value, the timer based PFM exit control circuit generating a PFM exit signal,
• wherein the timer based PFM exit control circuit asserts the PFM exit signal in response to the idle time being equal to or less than the timer threshold duration, and the boost switching regulator transitions out of the PFM mode and into the PWM mode in response to the PFM exit signal being asserted.