Pore sealing techniques for porous low-k dielectric interconnect
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Chi Ko, Pei-Wen Huang, Chun-Yi Lee, Kuang-Yuan Hsu, Tze-Liang Lee
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Abstract
The present disclosure relates to a method of forming pore sealing layer for porous low-k dielectric interconnects. The method is performed by removing hard mask layer before pore sealing and/or applying pore sealing layer before etching etch stop layer (ESL). These methods at least have advantages that aspect ratio is improved, line distortion introduced by the hard mask layer is avoided, and critical dimension is less affected by pore sealing layer.
Claims20
A semiconductor device comprising:
- a first conductive layer;
- an etch stop layer (ESL) over the first conductive layer;
- a porous low-k dielectric layer formed over the ESL layer;
- an opening extending downwardly through both the porous low-k dielectric layer and the ESL and stopping at the first conductive layer, wherein the opening defines both a dielectric sidewall in the porous low-k dielectric layer and an ESL sidewall in the ESL;
- a pore seal layer disposed on the dielectric sidewall but not covering the ESL sidewall;
- and
- a conductive material formed over the pore seal layer and filling the opening to form an interconnect structure to a second conductive layer over the porous low-k dielectric layer.
A semiconductor device comprising:
- first and second conductive layers over a semiconductor substrate;
- a porous low-k dielectric material arranged between the first and second conductive layers and including a trench and a via disposed therein, wherein the trench includes trench sidewalls extending downwardly from the second conductive layer to a trench bottom surface, and wherein the via includes via sidewalls extending downwardly from the trench bottom surface to the first conductive layer, the via sidewalls being more closely spaced than the trench sidewalls;
- a pore seal material disposed on the trench sidewalls and disposed on an upper region of the via sidewalls near the porous low-k dielectric layer but not disposed on a lower region of the via sidewalls near the first conductive layer;
- a conductive material formed over the pore seal material and filling the trench and via to electrically couple the first and second conductive layers to one another.
A method of forming a pore sealing for conductive interconnect structure on an integrated circuit die, the method comprising:
- providing a layer of porous low-k dielectric material on an etch stop layer;
- removing a selected portion of the dielectric material to form an opening therein;
- applying a pore seal layer to the opening;
- removing a selective portion of the etch stop layer downwardly from the opening, and concurrently removing the pore seal material from a bottom surface of the opening;
- and
- providing a conductive material in the opening downwardly to the bottom of the etch stop layer to form an interconnect structure.
The method according to claim 16, wherein the liner removal method etching is highly anisotropic, wherein a pressure lower than 40 mtorr and a bias power larger than 100 W are used.
The method according to claim 19, wherein the trench and the via are formed by a dual damascene method including via-first, trench first, or double patterning approach.
Dependencies are inferred from the claim text.