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US 2015/0091169 A1Published application
Semiconductor device and method for manufacturing semiconductor device
AssigneeRohm Co., Ltd.
InventorsOsamu MIYATA, Masaki KASAI, Shingo HIGUCHI
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Abstract
An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
Claims22
A semiconductor device comprising:
- a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;
- a stress relieving layer having an upper surface and a side surface provided on the passivation film;
- a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer;
- and
- a connecting metal layer provided on the upper surface of the stress relieving layer, the connecting metal layer having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed from a gap of the connecting metal layer;
- wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, and
- the sealing resin layer entirely covers the stress relieving layer, the passivation film and the connecting metal layer such that the sealing resin layer is formed on most part of the semiconductor device.
4 more elements
A semiconductor device comprising:
- a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;
- a stress relieving layer having an upper surface and a side surface provided on the passivation film;
- a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer;
- and
- a connecting metal member provided on the upper surface of the stress relieving layer, the connecting metal member having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed from a gap of the connecting metal member;
- wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, and
- the sealing resin layer entirely covers the stress relieving layer, the passivation film and the connecting metal member such that the sealing resin layer is formed on most part of the semiconductor device.
4 more elements
Dependencies are inferred from the claim text.