Stack-type semiconductor package

A stack-type semiconductor package comprising:

• a lower semiconductor package including a lower package substrate, lower lands on a top surface on the lower package substrate, a lower semiconductor chip on the top surface of the lower package substrate, and an encapsulant on the top surface of the lower package substrate, the encapsulant defining via holes that exposethe lower lands;
• an upper semiconductor package on the encapsulant, the upper semiconductor package including upper solder balls connected to a bottom surface of the upper semiconductor package;
• connection pads on the via holes and the encapsulant, the connection pads electrically connect the lower semiconductor package to the upper semiconductor package;
• and
• a metal layer pattern between the lower package substrate and the upper semiconductor package, the metal layer pattern surrounding the connection pads and being isolated from the connection pads.

A stack-type semiconductor package comprising:

• a lower package substrate;
• lower lands on the lower package substrate, the lower lands surrounding a portion of the substrate;
• a lower semiconductor chip on the portion of the lower package substrate;
• an encapsulant on the lower package substrate, the encapsulant surrounding the lower semiconductor chip and defining via holes that expose the lower lands;
• a metal layer pattern on the encapsulant over at least part of the portion of the lower package substrate;
• an upper semiconductor package on the lower package substrate, the upper semiconductor package including upper solder balls connected to a bottom surface of the upper semiconductor package;
• and
• connection pads electrically isolated from the metal layer pattern, the connection pads being electrically connected through the via holes to the lower lands, respectively, and the connection pads being electrically connected to the upper solder balls, respectively.