Multiple silicon trenches forming method for mems sealing cap wafer and etching mask structure thereof

A multiple silicon trenches forming method for MEMS sealing cap wafer, characterized in comprising:

• providing a MEMS sealing cap silicon substrate;
• forming a silicon oxide layer on the MEMS sealing cap silicon substrate as a first mask layer;
• photolithographing and etching the first mask layer to form a first etching window in the first mask layer;
• forming an aluminum layer or a silicon nitride layer on the first mask layer as a second mask layer;
• photolithographing and etching the second mask layer and the first mask layer to form a second etching window in the second mask layer and the first mask layer;
• forming a photoresist layer on the second mask layer as a third mask layer;
• photolithographing and etching the third mask layer, the second mask layer and the first mask layer to form a third etching window in the third mask layer, the second mask layer and the first mask layer;
• etching the MEMS sealing cap silicon substrate by using the third mask layer, the second mask layer and the first mask layer as a mask to form a first silicon trench with a depth of d3 in the MEMS sealing cap silicon substrate;
• removing the third mask layer;
• etching the MEMS sealing cap silicon substrate by using the second mask layer and the first mask layer as a mask to form a second silicon trench with a depth of d2 in the MEMS sealing cap silicon substrate, while the depth of the first silicon trench being deepened to d3+d2;
• removing the second mask layer;
• etching the MEMS sealing cap silicon substrate by using the first mask layer as a mask to form a third silicon trench with a depth of d1 in the MEMS sealing cap silicon substrate, while the depth of the first silicon trench being deepened to d3+d2+d1 and the depth of the second silicon trench being deepened to d2+d1;
• removing the first mask layer.