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US 2015/0091138 A1Published application
Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
AssigneeSpansion LLC
InventorFei WANG
Life of this patent
Estimating the term…
Abstract
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
Claims20
A semiconductor device, comprising:
- an active area having a plurality of active elements, each of the active elements being defined by a first trench overlapping with a via, each of the active elements including a first continuous metal filling disposed in the first trench and the via;
- and
- a die seal area defined by a second trench, a second continuous metal filling disposed in the second trench.
A semiconductor device, comprising:
- an active area having a plurality of active elements, each of the plurality of active elements including:
- a via;
- a first trench that overlaps the first via;
- and
- a first continuous metal filling disposed in the first trench and the first via;
- and
- a die seal area having a second trench, the die seal area including a second continuous metal filling disposed in the second trench.
4 more elements
A semiconductor device, comprising:
- a first area that includes:
- a via;
- a first trench that overlaps the first via;
- and
- a first continuous metal filling disposed in the first trench and the first via;
- and
- a second area that includes:
- a second trench;
- and
- a second continuous metal filling disposed in the second trench.
7 more elements
Dependencies are inferred from the claim text.