US 2015/0091131 A1 · POWER DISTRIBUTION FOR 3D SEMICONDUCTOR PACKAGE

Abstract

A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.

Claims20

Dependent claims

A structure comprising:

a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through an entire thickness of the laminate substrate;
a main die electrically coupled to a top of the laminate substrate;
a die stack electrically coupled to a bottom of the main die, the die stack comprising one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate;
and
an interposer positioned between and electrically coupled to a topmost chip of the die stack and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.

2 more elements

A method comprising:

electrically coupling a die stack to a main die;
electrically coupling the main die to a laminate substrate such that the die stack extends into an opening in the laminate substrate, the opening extending through an entire thickness of the laminate substrate;
attaching a lid to a top of the laminate substrate and a bottom of the main die;
electrically coupling an interposer to a topmost chip of the die stack, the interposer is within the opening such that a bottom surface of the interposer is substantially flush with a bottom surface of the laminate substrate;
and
electrically coupling a printed circuit board to the bottom of the laminate substrate and the bottom of the interposer such that the interposer forms an electrical path from the printed circuit board directly to the topmost chip of the die stack.

3 more elements

Dependencies are inferred from the claim text.

Power distribution for 3d semiconductor package

Life of this patent

Power distribution for 3d semiconductor package

Life of this patent

Abstract

Claims20