Heat dissipative electrical isolation/insulation structure for semiconductor devices and method of making

A method comprising:

• designating an active area of a substrate, the substrate including a target layer below the active area and at least one of an upper boundary layer between the target layer and the active area or a lower boundary layer below the target layer;
• forming the at least one of an upper boundary layer and a lower boundary layer, wherein the substrate includes silicon (Si), and the forming of the at least one of an upper boundary layer and a lower boundary layer includes adding germanium (Ge) to the substrate, the at least one of an upper boundary layer and a lower boundary layer thereby including silicon germanium (SiGe);
• forming at least one column of a substantially non-metallic structure material adjacent the active area from a top of the substrate to the target layer;
• and
• forming at least one lateral portion of the structure material to extend from the at least one column in the target layer.

A design structure readable by a machine used in design, manufacture, or simulation of an integrated circuit, the design structure comprising:

• an active area in at least one layer of a semiconductor device;
• a target layer below the active area;
• a lower boundary layer below the target layer and an upper boundary layer between the target layer and the active area;
• at least one column of a structure material extending from a top of the semiconductor device to the target layer;
• and
• at least one lateral portion of the structure material extending from the at least one column.