Semiconductor array having temperature-compensated breakdown voltage

A semiconductor array, comprising:

• a first metal layer arranged as a cathode;
• a highly n-doped silicon layer contacted with the first metal layer;
• an additional n-doped silicon layer contacted with the highly n-doped silicon layer;
• and
• an additional metal layer connected to the additional n-doped silicon layer and arranged as an anode, wherein:
• trenches are introduced into the additional n-doped silicon layer, the trenches having edge regions filled with a p-doped silicon layer, the trenches having an interior region filled with highly p-doped silicon,
• the edge regions of the trenches are contacted with the additional metal layer via a highly p-doped layer that forms an ohmic contact with the additional metal layer,
• the additional metal layer forms Schottky diodes with the additional n-doped layer,
• the highly p-doped internal regions of the trenches form npn transistors together with the edge regions of the trenches and the additional n-doped layer,
• the additional n-doped layer is arranged as a collector region,
• the highly p-doped internal regions of the trenches are arranged as emitter regions,
• the edge regions of the trenches function as base regions, and
• a limitation of reverse voltages for diode-forming collector-base junctions is determined by a punch-through effect.