Methods of forming finfet semiconductor devices using a replacement gate technique and the resulting devices

A method of forming a FinFET transistor above a semiconductor substrate, wherein the method comprises:

• performing at least one etching process so as to define a plurality of trenches in said substrate that define first and second fins in said substrate;
• forming a liner layer on said fins and in the trench between said first and second fins, said liner layer defining a recess;
• forming a layer of insulation material between said first and second fins and in said recess defined by said liner layer;
• forming a sacrificial gate structure above said first and second fins, said liner layer and said layer of insulating material;
• forming a sidewall spacer adjacent said sacrificial gate structure;
• removing said sacrificial gate structure so as to define a gate cavity between said sidewall spacers and to expose said liner layer and said layer of insulating material within said gate cavity;
• performing an etching process on said exposed portion of said liner layer within said gate cavity so as to remove portions of said liner layer positioned on each of said first and second fins, thereby resulting in the formation of a raised isolation post structure between said first and second fins and a first space and a second space between said raised isolation post structure and said first and second fins, respectively;
• and
• forming a replacement gate structure around a portion of each of said first and second fins and around a portion of said raised isolation post structure within said gate cavity, wherein at least portions of said replacement gate structure are positioned in said first and second spaces.

A device, comprising:

• at least first and second fins defined in a semiconductor substrate;
• a raised isolation post structure positioned between said first and second fins, wherein an upper surface of said raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface each of said first and second fins;
• a first space defined by a sidewall of said first fin and a first sidewall of said raised isolation post structure;
• a second space defined by a sidewall of said second fin and a second sidewall of said raised isolation post structure;
• and
• a gate structure positioned around a portion of each of said first and second fins and around a portion of said raised isolation post structure, wherein at least portions of said gate structure are positioned in said first and second spaces.