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US 2015/0091096 A1Published application
Semiconductor memory device
AssigneeSK hynix Inc.
InventorWan Cheul SHIN
Life of this patent
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Abstract
A semiconductor memory device includes a pipe channel layer formed on a semiconductor substrate, a first channel layer, a second channel layer and a third channel layer, connected with the pipe channel layer, first conductive layers stacked while surrounding the first channel layer, second conductive layers stacked while surrounding the second channel layer, and third conductive layers stacked while surrounding the third channel layer, wherein the first to third conductive layers are separately controlled.
Claims20
A semiconductor memory device, comprising:
- a pipe channel layer formed on a semiconductor substrate;
- a first channel layer, a second channel layer and a third channel layer, connected with the pipe channel layer;
- first conductive layers stacked while surrounding the first channel layer;
- second conductive layers stacked while surrounding the second channel layer;
- and
- third conductive layers stacked while surrounding the third channel layer,
- wherein the first to third conductive layers are separately controlled.
4 more elements
A semiconductor memory device, comprising:
- a pipe channel layer formed on a semiconductor substrate;
- a first drain side channel layer connecting the pipe channel layer and a bit line layer;
- a second drain side channel layer connecting the pipe channel layer and the bit line layer;
- and
- a source side channel layer connecting the pipe channel layer and a source line layer, and disposed between the first drain side channel layer and the second drain side channel layer.
2 more elements
A semiconductor memory device, comprising:
- a source side channel layer including a source selection transistor, source side memory cells, and a source side selection transistor, which are serially connected between a source line layer and a common node;
- a first drain side channel layer including a first drain selection transistor, first drain side memory cells, and a first drain side selection transistor, which are serially connected between a bit line layer and the common node;
- and
- a second drain side channel layer including a second drain selection transistor, second drain side memory cells, and a second drain side selection transistor, which are serially connected between the bit line layer and the common node,
- wherein the first drain side channel layer and the second drain side channel layer are connected in parallel between the bit line layer and the common node.
2 more elements
Dependencies are inferred from the claim text.