Integrated circuits with dual silicide contacts and methods for fabricating same
AssigneeGLOBAL FOUNDRIES Inc.
InventorsGuillaume Bouche, Shao Ming Koh, Jeremy A. Wahl, Andy Wei
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Abstract
Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.
Claims20
A method for fabricating an integrated circuit, the method comprising:
- providing a semiconductor substrate having PFET areas and NFET areas;
- selectively forming first silicide contacts from a first metal in the PFET areas;
- and
- selectively forming second silicide contacts from a second metal in the NFET areas, wherein the second metal is different from the first metal.
A method for fabricating an integrated circuit, the method comprising:
- providing a semiconductor substrate with a gate structure interposed between source/drain regions formed in a PFET area and a gate structure interposed between source/drain regions formed in an NFET area;
- forming a first metal layer on the source/drain regions in the PFET area;
- siliciding the first metal layer to form first silicide contacts on the source/drain regions in the PFET area;
- depositing a second metal layer over the gate structure and source/drain regions in the NFET area;
- and
- annealing the second metal layer to form second silicide contacts on the source/drain regions in the NFET area.
An integrated circuit comprising:
- a semiconductor substrate;
- a PFET device overlying the semiconductor substrate and including a PFET gate structure interposed between PFET source/drain regions;
- first contacts formed on the PFET source/drain regions and comprising a first metal silicide;
- an NFET device overlying the semiconductor substrate and including an NFET gate structure interposed between NFET source/drain regions;
- and
- second contacts formed on the NFET source/drain regions and comprising a second metal silicide different from the first metal silicide.
Dependencies are inferred from the claim text.