Power mosfet devices including embedded schottky diodes and methods of fabricating the same

A method of fabricating a semiconductor device, comprising:

• forming a first conductivity-type semiconductor layer on a semiconductor substrate;
• forming trenches in the semiconductor layer to define an active region between the trenches;
• forming a shield conductive pattern and a preliminary insulating structure surrounding the shield conductive pattern in each of the trenches, wherein the preliminary insulating structure is located at a lower level than an upper surface of the active region and partially fills the trenches;
• forming a body impurity region having a second conductivity-type different from the first conductivity-type by performing a body channel ion-implantation process to an upper portion of the active region,
• forming an insulating structure by partially etching the preliminary insulating structure after forming the body impurity region;
• forming a gate structure on the insulating structure;
• forming a first conductivity-type source impurity region in the upper portion of the active region, and a groove region sequentially passing through the source impurity region and the body impurity region after forming the gate structure, wherein the groove region has a tapered sidewall, the source impurity region includes first and second source regions spaced apart from each other on opposite sides of the groove region, and the body impurity region includes first and second body channel regions spaced apart from each other on the opposite sides of the groove region;
• and
• forming a front-side conductive pattern filling the groove region.

A semiconductor device, comprising:

• first and second vertical channel power MOSFET transistors arranged in a split-gate configuration in a semiconductor substrate;
• a groove in an active region between the first and second vertical channel power MOSFET transistors;
• a conductive pattern in the groove on the active region, the conductive pattern comprising a source contact for the first and second vertical channel power MOSFET transistors;
• and
• a vertical Schottky semiconductor region embedded in the groove beneath the conductive pattern between the vertical channel power MOSFET transistors.