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US 2015/0091077 A1Published application
Method of fabricating a non-volatile memory
AssigneeeMemory Technology Inc.
InventorsWein-Town Sun, Cheng-Yen Shen
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Abstract
A structure of a memory cell includes a substrate, a well, two source/drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell.
Claims18
A method of forming a memory cell, comprising:
- providing a substrate;
- forming a plurality of isolations on the substrate;
- forming a well on the substrate;
- forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate;
- forming a high-k gate dielectric layer on the stacked layer;
- forming a poly silicon gate on the high-k gate dielectric layer;
- forming at least two source/drain doped regions on the well;
- removing the poly silicon gate;
- and
- depositing a metal to a removed area of the poly silicon gate to form a metal gate.
7 more elements
A method of forming a memory cell, comprising:
- providing a substrate;
- forming a plurality of isolations on the substrate;
- forming a well on the substrate;
- forming a high-k gate dielectric layer on the well;
- forming a poly silicon gate on the high-k gate dielectric layer;
- forming at least two source/drain doped regions on the well;
- removing the poly silicon gate;
- forming a stacked layer comprising a tunneling layer, a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate;
- and
- depositing a metal to the removed area of the poly silicon gate to form a metal gate.
7 more elements
A memory cell, comprising:
- isolations formed on a substrate;
- a well formed directly on the substrate wherein the isolations define a region of the well;
- at least two source/drain doped regions formed on the well;
- a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well;
- a high-k gate dielectric layer formed on the stacked layer;
- and
- a metal gate formed on the high-k gate dielectric layer.
4 more elements
Dependencies are inferred from the claim text.