Nonvolatile memory structure
AssigneeeMemory Technology Inc.
InventorsTe-Hsun Hsu, Wei-Ren Chen, Hsuen-Wei Chen, Mu-Ying Tsao, Ying-Je Chen
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Abstract
A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
Claims25
A nonvolatile memory cell unit, comprising:
- a P type substrate;
- an N well in the P type substrate;
- and
- a PMOS storage transistor disposed on the N well, wherein the PMOS storage transistor comprises a floating gate, a P+ drain doping region, a common P+ doping region, a floating gate dielectric layer between the floating gate and the N well, a floating gate channel between the P+ drain doping region and the common P+ doping region, and an auxiliary gate disposed in close proximity to one side of the floating gate, wherein a gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
A nonvolatile memory cell unit, comprising:
- a semiconductor substrate having a first conductivity type;
- a well of a second conductivity type in the semiconductor substrate;
- a select transistor disposed on the well;
- and
- a storage transistor disposed on the well and being serially connected to the select transistor, wherein the storage transistor comprises a juxtaposed dual-gate structure that is disposed on a channel region of the storage transistor.
Dependencies are inferred from the claim text.