Nonvolatile memory structure and fabrication method thereof
AssigneeeMemory Technology Inc.
InventorsYi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Abstract
According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
Claims22
A single-poly nonvolatile memory (NVM) cell, comprising:
- a select transistor on a first well of a semiconductor substrate, wherein the select transistor comprises a select gate, a first gate oxide layer between the select gate and the semiconductor substrate, a first source/drain doping region in the first well, and a second source/drain doping region spaced apart from the first source/drain doping region;
- a floating gate transistor on the first well serially connected to the select transistor, wherein the PMOS floating gate transistor comprises a floating gate, a second gate oxide layer between the floating gate and the semiconductor substrate, the second source/drain doping region commonly shared by the select transistor, and a third source/drain doping region spaced apart from the second source/drain doping region;
- a first salicide layer on the first source/drain doping region;
- a protector oxide layer covering and being in direct contact with the floating gate;
- and
- a contact etch stop layer on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
Dependencies are inferred from the claim text.