Memory Devices and Method of Forming Same

A method comprising:

• forming a control gate structure over a substrate;
• forming an Oxide-Silicon-Oxide layer over the control gate structure;
• depositing a memory gate layer over the Oxide-Silicon-Oxide layer;
• depositing a memory gate mask layer over the memory gate layer;
• forming a first memory gate structure and a second memory gate structure through a first etching process, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure;
• forming first spacers along sidewalls of the first memory gate structure and the second memory gate structure;
• removing the second memory gate structure through a second etching process;
• applying a third etching process to a top oxide layer of the Oxide-Silicon-Oxide layer;
• applying a fourth etching process to a silicon dot layer of the Oxide-Silicon-Oxide layer;
• forming a second spacer over the memory gate structure;
• and
• forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure.

A method comprising:

• forming a control gate structure comprising a control gate dielectric layer over a substrate and a control gate electrode over the control gate dielectric layer;
• depositing a charge storage layer over a control gate structure, wherein the charge storage layer comprise a first oxide layer, a silicon dot layer and a second oxide layer;
• depositing a memory gate layer over the charge storage layer, wherein a top surface of the memory gate layer is lower than a top surface of the second oxide layer;
• depositing a gate mask layer over the memory gate layer;
• applying a first etching process to the gate mask layer and the memory gate layer until a top surface of the second oxide layer is exposed, wherein a remaining portion of the gate mask layer is over a remaining portion of the memory gate layer after performing the first etching process;
• forming a thin spacer layer along a sidewall of the remaining portion of the memory gate layer and a sidewall of the remaining portion of the gate mask layer;
• applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the remaining portion of the memory gate layer is located between the thin spacer layer and the L-shaped charge storage layer;
• and
• forming a top spacer layer over the remaining portion of the gate mask layer and the L-shaped charge storage layer.